The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/interconnect/fsl,imx8m-noc.yaml

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    1 # SPDX-License-Identifier: GPL-2.0
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Generic i.MX bus frequency device
    8 
    9 maintainers:
   10   - Peng Fan <peng.fan@nxp.com>
   11 
   12 description: |
   13   The i.MX SoC family has multiple buses for which clock frequency (and
   14   sometimes voltage) can be adjusted.
   15 
   16   Some of those buses expose register areas mentioned in the memory maps as GPV
   17   ("Global Programmers View") but not all. Access to this area might be denied
   18   for normal (non-secure) world.
   19 
   20   The buses are based on externally licensed IPs such as ARM NIC-301 and
   21   Arteris FlexNOC but DT bindings are specific to the integration of these bus
   22   interconnect IPs into imx SOCs.
   23 
   24 properties:
   25   compatible:
   26     oneOf:
   27       - items:
   28           - enum:
   29               - fsl,imx8mm-nic
   30               - fsl,imx8mn-nic
   31               - fsl,imx8mp-nic
   32               - fsl,imx8mq-nic
   33           - const: fsl,imx8m-nic
   34       - items:
   35           - enum:
   36               - fsl,imx8mm-noc
   37               - fsl,imx8mn-noc
   38               - fsl,imx8mp-noc
   39               - fsl,imx8mq-noc
   40           - const: fsl,imx8m-noc
   41       - const: fsl,imx8m-nic
   42 
   43   reg:
   44     maxItems: 1
   45 
   46   clocks:
   47     maxItems: 1
   48 
   49   operating-points-v2: true
   50   opp-table: true
   51 
   52   fsl,ddrc:
   53     $ref: "/schemas/types.yaml#/definitions/phandle"
   54     description:
   55       Phandle to DDR Controller.
   56 
   57   '#interconnect-cells':
   58     description:
   59       If specified then also act as an interconnect provider. Should only be
   60       set once per soc on the main noc.
   61     const: 1
   62 
   63 required:
   64   - compatible
   65   - clocks
   66 
   67 additionalProperties: false
   68 
   69 examples:
   70   - |
   71     #include <dt-bindings/clock/imx8mm-clock.h>
   72     #include <dt-bindings/interconnect/imx8mm.h>
   73     #include <dt-bindings/interrupt-controller/arm-gic.h>
   74 
   75     noc: interconnect@32700000 {
   76         compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc";
   77         reg = <0x32700000 0x100000>;
   78         clocks = <&clk IMX8MM_CLK_NOC>;
   79         #interconnect-cells = <1>;
   80         fsl,ddrc = <&ddrc>;
   81 
   82         operating-points-v2 = <&noc_opp_table>;
   83         noc_opp_table: opp-table {
   84             compatible = "operating-points-v2";
   85 
   86             opp-133333333 {
   87                 opp-hz = /bits/ 64 <133333333>;
   88             };
   89             opp-800000000 {
   90                 opp-hz = /bits/ 64 <800000000>;
   91             };
   92         };
   93     };
   94 
   95     ddrc: memory-controller@3d400000 {
   96         compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
   97         reg = <0x3d400000 0x400000>;
   98         clock-names = "core", "pll", "alt", "apb";
   99         clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
  100                  <&clk IMX8MM_DRAM_PLL>,
  101                  <&clk IMX8MM_CLK_DRAM_ALT>,
  102                  <&clk IMX8MM_CLK_DRAM_APB>;
  103     };

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