arm,gic.yaml

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    1 # SPDX-License-Identifier: GPL-2.0
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: ARM Generic Interrupt Controller v1 and v2
    8 
    9 maintainers:
   10   - Marc Zyngier <marc.zyngier@arm.com>
   11 
   12 description: |+
   13   ARM SMP cores are often associated with a GIC, providing per processor
   14   interrupts (PPI), shared processor interrupts (SPI) and software
   15   generated interrupts (SGI).
   16 
   17   Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
   18   Secondary GICs are cascaded into the upward interrupt controller and do not
   19   have PPIs or SGIs.
   20 
   21 allOf:
   22   - $ref: /schemas/interrupt-controller.yaml#
   23 
   24 properties:
   25   compatible:
   26     oneOf:
   27       - items:
   28           - enum:
   29               - arm,arm11mp-gic
   30               - arm,cortex-a15-gic
   31               - arm,cortex-a7-gic
   32               - arm,cortex-a5-gic
   33               - arm,cortex-a9-gic
   34               - arm,eb11mp-gic
   35               - arm,gic-400
   36               - arm,pl390
   37               - arm,tc11mp-gic
   38               - qcom,msm-8660-qgic
   39               - qcom,msm-qgic2
   40 
   41       - items:
   42           - const: arm,gic-400
   43           - enum:
   44               - arm,cortex-a15-gic
   45               - arm,cortex-a7-gic
   46 
   47       - items:
   48           - const: arm,arm1176jzf-devchip-gic
   49           - const: arm,arm11mp-gic
   50 
   51       - items:
   52           - const: brcm,brahma-b15-gic
   53           - const: arm,cortex-a15-gic
   54 
   55       - oneOf:
   56           - const: nvidia,tegra210-agic
   57           - items:
   58               - enum:
   59                   - nvidia,tegra186-agic
   60                   - nvidia,tegra194-agic
   61                   - nvidia,tegra234-agic
   62               - const: nvidia,tegra210-agic
   63 
   64   interrupt-controller: true
   65 
   66   "#address-cells":
   67     enum: [ 0, 1 ]
   68   "#size-cells":
   69     const: 1
   70 
   71   "#interrupt-cells":
   72     const: 3
   73     description: |
   74       The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
   75       interrupts.
   76 
   77       The 2nd cell contains the interrupt number for the interrupt type.
   78       SPI interrupts are in the range [0-987].  PPI interrupts are in the
   79       range [0-15].
   80 
   81       The 3rd cell is the flags, encoded as follows:
   82         bits[3:0] trigger type and level flags.
   83           1 = low-to-high edge triggered
   84           2 = high-to-low edge triggered (invalid for SPIs)
   85           4 = active high level-sensitive
   86           8 = active low level-sensitive (invalid for SPIs).
   87         bits[15:8] PPI interrupt cpu mask.  Each bit corresponds to each of
   88         the 8 possible cpus attached to the GIC.  A bit set to '1' indicated
   89         the interrupt is wired to that CPU.  Only valid for PPI interrupts.
   90         Also note that the configurability of PPI interrupts is IMPLEMENTATION
   91         DEFINED and as such not guaranteed to be present (most SoC available
   92         in 2014 seem to ignore the setting of this flag and use the hardware
   93         default value).
   94 
   95   reg:
   96     description: |
   97       Specifies base physical address(s) and size of the GIC registers. The
   98       first region is the GIC distributor register base and size. The 2nd region
   99       is the GIC cpu interface register base and size.
  100 
  101       For GICv2 with virtualization extensions, additional regions are
  102       required for specifying the base physical address and size of the VGIC
  103       registers. The first additional region is the GIC virtual interface
  104       control register base and size. The 2nd additional region is the GIC
  105       virtual cpu interface register base and size.
  106     minItems: 2
  107     maxItems: 4
  108 
  109   ranges: true
  110 
  111   interrupts:
  112     description: Interrupt source of the parent interrupt controller on
  113       secondary GICs, or VGIC maintenance interrupt on primary GIC (see
  114       below).
  115     maxItems: 1
  116 
  117   cpu-offset:
  118     description: per-cpu offset within the distributor and cpu interface
  119       regions, used when the GIC doesn't have banked registers. The offset
  120       is cpu-offset * cpu-nr.
  121     $ref: /schemas/types.yaml#/definitions/uint32
  122 
  123   clocks:
  124     minItems: 1
  125     maxItems: 2
  126 
  127   clock-names:
  128     description: List of names for the GIC clock input(s). Valid clock names
  129       depend on the GIC variant.
  130     oneOf:
  131       - const: ic_clk # for "arm,arm11mp-gic"
  132       - const: PERIPHCLKEN # for "arm,cortex-a15-gic"
  133       - items: # for "arm,cortex-a9-gic"
  134           - const: PERIPHCLK
  135           - const: PERIPHCLKEN
  136       - const: clk # for "arm,gic-400" and "nvidia,tegra210"
  137       - const: gclk #for "arm,pl390"
  138 
  139   power-domains:
  140     maxItems: 1
  141 
  142   resets:
  143     maxItems: 1
  144 
  145 required:
  146   - compatible
  147   - reg
  148 
  149 patternProperties:
  150   "^v2m@[0-9a-f]+$":
  151     type: object
  152     description: |
  153       * GICv2m extension for MSI/MSI-x support (Optional)
  154 
  155       Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
  156       This is enabled by specifying v2m sub-node(s).
  157 
  158     properties:
  159       compatible:
  160         const: arm,gic-v2m-frame
  161 
  162       msi-controller: true
  163 
  164       reg:
  165         maxItems: 1
  166         description: GICv2m MSI interface register base and size
  167 
  168       arm,msi-base-spi:
  169         description: When the MSI_TYPER register contains an incorrect value,
  170           this property should contain the SPI base of the MSI frame, overriding
  171           the HW value.
  172         $ref: /schemas/types.yaml#/definitions/uint32
  173 
  174       arm,msi-num-spis:
  175         description: When the MSI_TYPER register contains an incorrect value,
  176           this property should contain the number of SPIs assigned to the
  177           frame, overriding the HW value.
  178         $ref: /schemas/types.yaml#/definitions/uint32
  179 
  180     required:
  181       - compatible
  182       - msi-controller
  183       - reg
  184 
  185     additionalProperties: false
  186 
  187 additionalProperties: false
  188 
  189 examples:
  190   - |
  191     // GICv1
  192     intc: interrupt-controller@fff11000 {
  193       compatible = "arm,cortex-a9-gic";
  194       #interrupt-cells = <3>;
  195       #address-cells = <1>;
  196       interrupt-controller;
  197       reg = <0xfff11000 0x1000>,
  198             <0xfff10100 0x100>;
  199     };
  200 
  201   - |
  202     // GICv2
  203     interrupt-controller@2c001000 {
  204       compatible = "arm,cortex-a15-gic";
  205       #interrupt-cells = <3>;
  206       interrupt-controller;
  207       reg = <0x2c001000 0x1000>,
  208             <0x2c002000 0x2000>,
  209             <0x2c004000 0x2000>,
  210             <0x2c006000 0x2000>;
  211       interrupts = <1 9 0xf04>;
  212     };
  213 
  214   - |
  215     // GICv2m extension for MSI/MSI-x support
  216     interrupt-controller@e1101000 {
  217       compatible = "arm,gic-400";
  218       #interrupt-cells = <3>;
  219       #address-cells = <1>;
  220       #size-cells = <1>;
  221       interrupt-controller;
  222       interrupts = <1 8 0xf04>;
  223       ranges = <0 0xe1100000 0x100000>;
  224       reg = <0xe1110000 0x01000>,
  225             <0xe112f000 0x02000>,
  226             <0xe1140000 0x10000>,
  227             <0xe1160000 0x10000>;
  228 
  229       v2m0: v2m@80000 {
  230         compatible = "arm,gic-v2m-frame";
  231         msi-controller;
  232         reg = <0x80000 0x1000>;
  233       };
  234 
  235       //...
  236 
  237       v2mN: v2m@90000 {
  238         compatible = "arm,gic-v2m-frame";
  239         msi-controller;
  240         reg = <0x90000 0x1000>;
  241       };
  242     };
  243 ...

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