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     1 BCM2836 per-CPU interrupt controller
    2 
    3 The BCM2836 has a per-cpu interrupt controller for the timer, PMU
    4 events, and SMP IPIs.  One of the CPUs may receive interrupts for the
    5 peripheral (GPU) events, which chain to the BCM2835-style interrupt
    6 controller.
    7 
    8 Required properties:
    9 
   10 - compatible:           Should be "brcm,bcm2836-l1-intc"
   11 - reg:                  Specifies base physical address and size of the
   12                           registers
   13 - interrupt-controller: Identifies the node as an interrupt controller
   14 - #interrupt-cells:     Specifies the number of cells needed to encode an
   15                           interrupt source. The value shall be 2
   16 
   17 Please refer to interrupts.txt in this directory for details of the common
   18 Interrupt Controllers bindings used by client devices.
   19 
   20 The interrupt sources are as follows:
   21 
   22 0: CNTPSIRQ
   23 1: CNTPNSIRQ
   24 2: CNTHPIRQ
   25 3: CNTVIRQ
   26 8: GPU_FAST
   27 9: PMU_FAST
   28 
   29 Example:
   30 
   31 local_intc: local_intc {
   32         compatible = "brcm,bcm2836-l1-intc";
   33         reg = <0x40000000 0x100>;
   34         interrupt-controller;
   35         #interrupt-cells = <2>;
   36         interrupt-parent = <&local_intc>;
   37 };
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