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     1 Broadcom BCM3380-style Level 1 / Level 2 interrupt controller
    2 
    3 This interrupt controller shows up in various forms on many BCM338x/BCM63xx
    4 chipsets.  It has the following properties:
    5 
    6 - outputs a single interrupt signal to its interrupt controller parent
    7 
    8 - contains one or more enable/status word pairs, which often appear at
    9   different offsets in different blocks
   10 
   11 - no atomic set/clear operations
   12 
   13 Required properties:
   14 
   15 - compatible: should be "brcm,bcm3380-l2-intc"
   16 - reg: specifies one or more enable/status pairs, in the following format:
   17   <enable_reg 0x4 status_reg 0x4>...
   18 - interrupt-controller: identifies the node as an interrupt controller
   19 - #interrupt-cells: specifies the number of cells needed to encode an interrupt
   20   source, should be 1.
   21 - interrupts: specifies the interrupt line in the interrupt-parent controller
   22   node, valid values depend on the type of parent interrupt controller
   23 
   24 Optional properties:
   25 
   26 - brcm,irq-can-wake: if present, this means the L2 controller can be used as a
   27   wakeup source for system suspend/resume.
   28 
   29 Example:
   30 
   31 irq0_intc: interrupt-controller@10000020 {
   32         compatible = "brcm,bcm3380-l2-intc";
   33         reg = <0x10000024 0x4 0x1000002c 0x4>,
   34               <0x10000020 0x4 0x10000028 0x4>;
   35         interrupt-controller;
   36         #interrupt-cells = <1>;
   37         interrupt-parent = <&cpu_intc>;
   38         interrupts = <2>;
   39 };
Cache object: 311ccb13f605976a5e295c214d20ae27 
 
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