brcm,bcm7038-l1-intc.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7038-l1-intc.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Broadcom BCM7038-style Level 1 interrupt controller
    8 
    9 description: >
   10   This block is a first level interrupt controller that is typically connected
   11   directly to one of the HW INT lines on each CPU.  Every BCM7xxx set-top chip
   12   since BCM7038 has contained this hardware.
   13 
   14   Key elements of the hardware design include:
   15 
   16    - 64, 96, 128, or 160 incoming level IRQ lines
   17 
   18    - Most onchip peripherals are wired directly to an L1 input
   19 
   20    - A separate instance of the register set for each CPU, allowing individual
   21      peripheral IRQs to be routed to any CPU
   22 
   23    - Atomic mask/unmask operations
   24 
   25    - No polarity/level/edge settings
   26 
   27    - No FIFO or priority encoder logic; software is expected to read all
   28      2-5 status words to determine which IRQs are pending
   29 
   30    If multiple reg ranges and interrupt-parent entries are present on an SMP
   31    system, the driver will allow IRQ SMP affinity to be set up through the
   32    /proc/irq/ interface.  In the simplest possible configuration, only one
   33    reg range and one interrupt-parent is needed.
   34 
   35 maintainers:
   36   - Florian Fainelli <f.fainelli@gmail.com>
   37 
   38 allOf:
   39   - $ref: /schemas/interrupt-controller.yaml#
   40 
   41 properties:
   42   compatible:
   43     const: brcm,bcm7038-l1-intc
   44 
   45   reg:
   46     description: >
   47       Specifies the base physical address and size of the registers
   48       the number of supported IRQs is inferred from the size argument
   49 
   50   interrupt-controller: true
   51 
   52   "#interrupt-cells":
   53     const: 1
   54 
   55   interrupts:
   56     description: >
   57      Specifies the interrupt line(s) in the interrupt-parent controller node;
   58      valid values depend on the type of parent interrupt controller
   59 
   60   brcm,irq-can-wake:
   61     type: boolean
   62     description: >
   63       If present, this means the L1 controller can be used as a
   64       wakeup source for system suspend/resume.
   65 
   66   brcm,int-fwd-mask:
   67     $ref: /schemas/types.yaml#/definitions/uint32-array
   68     description:
   69       If present, a bit mask to indicate which interrupts have already been
   70       configured by the firmware and should be left unmanaged. This should
   71       have one 32-bit word per status/set/clear/mask group.
   72 
   73 required:
   74   - compatible
   75   - reg
   76   - interrupt-controller
   77   - "#interrupt-cells"
   78   - interrupts
   79 
   80 additionalProperties: false
   81 
   82 examples:
   83   - |
   84     periph_intc: interrupt-controller@1041a400 {
   85       compatible = "brcm,bcm7038-l1-intc";
   86       reg = <0x1041a400 0x30>, <0x1041a600 0x30>;
   87       interrupt-controller;
   88       #interrupt-cells = <1>;
   89       interrupt-parent = <&cpu_intc>;
   90       interrupts = <2>, <3>;
   91     };

Cache object: 170cdb8ae11f8ef760d7f865b94ff317

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sys/contrib/device-tree/Bindings/interrupt-controller/brcm,bcm7038-l1-intc.yaml