The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/interrupt-controller/microchip,pic32-evic.txt

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    1 Microchip PIC32 Interrupt Controller
    2 ====================================
    3 
    4 The Microchip PIC32 contains an Enhanced Vectored Interrupt Controller (EVIC).
    5 It handles all internal and external interrupts. This controller exists outside
    6 of the CPU and is the arbitrator of all interrupts (including interrupts from
    7 the CPU itself) before they are presented to the CPU.
    8 
    9 External interrupts have a software configurable edge polarity. Non external
   10 interrupts have a type and polarity that is determined by the source of the
   11 interrupt.
   12 
   13 Required properties
   14 -------------------
   15 
   16 - compatible: Should be "microchip,pic32mzda-evic"
   17 - reg: Specifies physical base address and size of register range.
   18 - interrupt-controller: Identifies the node as an interrupt controller.
   19 - #interrupt cells: Specifies the number of cells used to encode an interrupt
   20   source connected to this controller. The value shall be 2 and interrupt
   21   descriptor shall have the following format:
   22 
   23         <hw_irq irq_type>
   24 
   25   hw_irq - represents the hardware interrupt number as in the data sheet.
   26   irq_type - is used to describe the type and polarity of an interrupt. For
   27   internal interrupts use IRQ_TYPE_EDGE_RISING for non persistent interrupts and
   28   IRQ_TYPE_LEVEL_HIGH for persistent interrupts. For external interrupts use
   29   IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING to select the desired polarity.
   30 
   31 Optional properties
   32 -------------------
   33 - microchip,external-irqs: u32 array of external interrupts with software
   34   polarity configuration. This array corresponds to the bits in the INTCON
   35   SFR.
   36 
   37 Example
   38 -------
   39 
   40 evic: interrupt-controller@1f810000 {
   41         compatible = "microchip,pic32mzda-evic";
   42         interrupt-controller;
   43         #interrupt-cells = <2>;
   44         reg = <0x1f810000 0x1000>;
   45         microchip,external-irqs = <3 8 13 18 23>;
   46 };
   47 
   48 Each device/peripheral must request its interrupt line with the associated type
   49 and polarity.
   50 
   51 Internal interrupt DTS snippet
   52 ------------------------------
   53 
   54 device@1f800000 {
   55         ...
   56         interrupts = <113 IRQ_TYPE_LEVEL_HIGH>;
   57         ...
   58 };
   59 
   60 External interrupt DTS snippet
   61 ------------------------------
   62 
   63 device@1f800000 {
   64         ...
   65         interrupts = <3 IRQ_TYPE_EDGE_RISING>;
   66         ...
   67 };

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