The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)

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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/interrupt-controller/renesas,rza1-irqc.txt

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    1 DT bindings for the Renesas RZ/A1 Interrupt Controller
    2 
    3 The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas
    4 RZ/A1 and RZ/A2 SoCs:
    5   - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI
    6     interrupts,
    7   - NMI edge select.
    8 
    9 Required properties:
   10   - compatible: Must be "renesas,<soctype>-irqc", and "renesas,rza1-irqc" as
   11                 fallback.
   12                 Examples with soctypes are:
   13                   - "renesas,r7s72100-irqc" (RZ/A1H)
   14                   - "renesas,r7s9210-irqc" (RZ/A2M)
   15   - #interrupt-cells: Must be 2 (an interrupt index and flags, as defined
   16                                  in interrupts.txt in this directory)
   17   - #address-cells: Must be zero
   18   - interrupt-controller: Marks the device as an interrupt controller
   19   - reg: Base address and length of the memory resource used by the interrupt
   20          controller
   21   - interrupt-map: Specifies the mapping from external interrupts to GIC
   22                    interrupts
   23   - interrupt-map-mask: Must be <7 0>
   24 
   25 Example:
   26 
   27         irqc: interrupt-controller@fcfef800 {
   28                 compatible = "renesas,r7s72100-irqc", "renesas,rza1-irqc";
   29                 #interrupt-cells = <2>;
   30                 #address-cells = <0>;
   31                 interrupt-controller;
   32                 reg = <0xfcfef800 0x6>;
   33                 interrupt-map =
   34                         <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
   35                         <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
   36                         <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
   37                         <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
   38                         <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
   39                         <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
   40                         <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
   41                         <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
   42                 interrupt-map-mask = <7 0>;
   43         };

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