qcom,iommu.txt

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    1 * QCOM IOMMU v1 Implementation
    2 
    3 Qualcomm "B" family devices which are not compatible with arm-smmu have
    4 a similar looking IOMMU but without access to the global register space,
    5 and optionally requiring additional configuration to route context irqs
    6 to non-secure vs secure interrupt line.
    7 
    8 ** Required properties:
    9 
   10 - compatible       : Should be one of:
   11 
   12                         "qcom,msm8916-iommu"
   13 
   14                      Followed by "qcom,msm-iommu-v1".
   15 
   16 - clock-names      : Should be a pair of "iface" (required for IOMMUs
   17                      register group access) and "bus" (required for
   18                      the IOMMUs underlying bus access).
   19 
   20 - clocks           : Phandles for respective clocks described by
   21                      clock-names.
   22 
   23 - #address-cells   : must be 1.
   24 
   25 - #size-cells      : must be 1.
   26 
   27 - #iommu-cells     : Must be 1.  Index identifies the context-bank #.
   28 
   29 - ranges           : Base address and size of the iommu context banks.
   30 
   31 - qcom,iommu-secure-id  : secure-id.
   32 
   33 - List of sub-nodes, one per translation context bank.  Each sub-node
   34   has the following required properties:
   35 
   36   - compatible     : Should be one of:
   37         - "qcom,msm-iommu-v1-ns"  : non-secure context bank
   38         - "qcom,msm-iommu-v1-sec" : secure context bank
   39   - reg            : Base address and size of context bank within the iommu
   40   - interrupts     : The context fault irq.
   41 
   42 ** Optional properties:
   43 
   44 - reg              : Base address and size of the SMMU local base, should
   45                      be only specified if the iommu requires configuration
   46                      for routing of context bank irq's to secure vs non-
   47                      secure lines.  (Ie. if the iommu contains secure
   48                      context banks)
   49 
   50 
   51 ** Examples:
   52 
   53         apps_iommu: iommu@1e20000 {
   54                 #address-cells = <1>;
   55                 #size-cells = <1>;
   56                 #iommu-cells = <1>;
   57                 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
   58                 ranges = <0 0x1e20000 0x40000>;
   59                 reg = <0x1ef0000 0x3000>;
   60                 clocks = <&gcc GCC_SMMU_CFG_CLK>,
   61                          <&gcc GCC_APSS_TCU_CLK>;
   62                 clock-names = "iface", "bus";
   63                 qcom,iommu-secure-id = <17>;
   64 
   65                 // mdp_0:
   66                 iommu-ctx@4000 {
   67                         compatible = "qcom,msm-iommu-v1-ns";
   68                         reg = <0x4000 0x1000>;
   69                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
   70                 };
   71 
   72                 // venus_ns:
   73                 iommu-ctx@5000 {
   74                         compatible = "qcom,msm-iommu-v1-sec";
   75                         reg = <0x5000 0x1000>;
   76                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
   77                 };
   78         };
   79 
   80         gpu_iommu: iommu@1f08000 {
   81                 #address-cells = <1>;
   82                 #size-cells = <1>;
   83                 #iommu-cells = <1>;
   84                 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
   85                 ranges = <0 0x1f08000 0x10000>;
   86                 clocks = <&gcc GCC_SMMU_CFG_CLK>,
   87                          <&gcc GCC_GFX_TCU_CLK>;
   88                 clock-names = "iface", "bus";
   89                 qcom,iommu-secure-id = <18>;
   90 
   91                 // gfx3d_user:
   92                 iommu-ctx@1000 {
   93                         compatible = "qcom,msm-iommu-v1-ns";
   94                         reg = <0x1000 0x1000>;
   95                         interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
   96                 };
   97 
   98                 // gfx3d_priv:
   99                 iommu-ctx@2000 {
  100                         compatible = "qcom,msm-iommu-v1-ns";
  101                         reg = <0x2000 0x1000>;
  102                         interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
  103                 };
  104         };
  105 
  106         ...
  107 
  108         venus: video-codec@1d00000 {
  109                 ...
  110                 iommus = <&apps_iommu 5>;
  111         };
  112 
  113         mdp: mdp@1a01000 {
  114                 ...
  115                 iommus = <&apps_iommu 4>;
  116         };
  117 
  118         gpu@1c00000 {
  119                 ...
  120                 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
  121         };

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