renesas,ipmmu-vmsa.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Renesas VMSA-Compatible IOMMU
    8 
    9 maintainers:
   10   - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
   11 
   12 description:
   13   The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
   14   It provides address translation for bus masters outside of the CPU, each
   15   connected to the IPMMU through a port called micro-TLB.
   16 
   17 properties:
   18   compatible:
   19     oneOf:
   20       - items:
   21           - enum:
   22               - renesas,ipmmu-r8a73a4  # R-Mobile APE6
   23               - renesas,ipmmu-r8a7742  # RZ/G1H
   24               - renesas,ipmmu-r8a7743  # RZ/G1M
   25               - renesas,ipmmu-r8a7744  # RZ/G1N
   26               - renesas,ipmmu-r8a7745  # RZ/G1E
   27               - renesas,ipmmu-r8a7790  # R-Car H2
   28               - renesas,ipmmu-r8a7791  # R-Car M2-W
   29               - renesas,ipmmu-r8a7793  # R-Car M2-N
   30               - renesas,ipmmu-r8a7794  # R-Car E2
   31           - const: renesas,ipmmu-vmsa  # R-Mobile APE6 or R-Car Gen2 or RZ/G1
   32       - items:
   33           - enum:
   34               - renesas,ipmmu-r8a774a1 # RZ/G2M
   35               - renesas,ipmmu-r8a774b1 # RZ/G2N
   36               - renesas,ipmmu-r8a774c0 # RZ/G2E
   37               - renesas,ipmmu-r8a774e1 # RZ/G2H
   38               - renesas,ipmmu-r8a7795  # R-Car H3
   39               - renesas,ipmmu-r8a7796  # R-Car M3-W
   40               - renesas,ipmmu-r8a77961 # R-Car M3-W+
   41               - renesas,ipmmu-r8a77965 # R-Car M3-N
   42               - renesas,ipmmu-r8a77970 # R-Car V3M
   43               - renesas,ipmmu-r8a77980 # R-Car V3H
   44               - renesas,ipmmu-r8a77990 # R-Car E3
   45               - renesas,ipmmu-r8a77995 # R-Car D3
   46               - renesas,ipmmu-r8a779a0 # R-Car V3U
   47       - items:
   48           - enum:
   49               - renesas,ipmmu-r8a779f0 # R-Car S4-8
   50           - const: renesas,rcar-gen4-ipmmu-vmsa  # R-Car Gen4
   51 
   52   reg:
   53     maxItems: 1
   54 
   55   interrupts:
   56     minItems: 1
   57     description:
   58       Specifiers for the MMU fault interrupts. Not required for cache IPMMUs.
   59     items:
   60       - description: non-secure mode
   61       - description: secure mode if supported
   62 
   63   '#iommu-cells':
   64     const: 1
   65     description:
   66       The number of the micro-TLB that the device is connected to.
   67 
   68   power-domains:
   69     maxItems: 1
   70 
   71   renesas,ipmmu-main:
   72     $ref: /schemas/types.yaml#/definitions/phandle-array
   73     items:
   74       - items:
   75           - description: phandle to main IPMMU
   76           - description: the interrupt bit number associated with the particular
   77               cache IPMMU device. The interrupt bit number needs to match the main
   78               IPMMU IMSSTR register. Only used by cache IPMMU instances.
   79     description:
   80       Reference to the main IPMMU phandle plus 1 cell. The cell is
   81       the interrupt bit number associated with the particular cache IPMMU
   82       device. The interrupt bit number needs to match the main IPMMU IMSSTR
   83       register. Only used by cache IPMMU instances.
   84 
   85 required:
   86   - compatible
   87   - reg
   88   - '#iommu-cells'
   89 
   90 oneOf:
   91   - required:
   92       - interrupts
   93   - required:
   94       - renesas,ipmmu-main
   95 
   96 additionalProperties: false
   97 
   98 allOf:
   99   - if:
  100       properties:
  101         compatible:
  102           not:
  103             contains:
  104               const: renesas,ipmmu-vmsa
  105     then:
  106       required:
  107         - power-domains
  108 
  109 examples:
  110   - |
  111     #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
  112     #include <dt-bindings/interrupt-controller/arm-gic.h>
  113     #include <dt-bindings/power/r8a7791-sysc.h>
  114 
  115     ipmmu_mx: iommu@fe951000 {
  116         compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
  117         reg = <0xfe951000 0x1000>;
  118         interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
  119                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
  120         #iommu-cells = <1>;
  121     };

Cache object: 6ae0fea0f121a0460d8e03e2a70ae273

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/iommu/renesas,ipmmu-vmsa.yaml

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/iommu/renesas,ipmmu-vmsa.yaml