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     1 Rockchip IOMMU
    2 ==============
    3 
    4 A Rockchip DRM iommu translates io virtual addresses to physical addresses for
    5 its master device.  Each slave device is bound to a single master device, and
    6 shares its clocks, power domain and irq.
    7 
    8 Required properties:
    9 - compatible      : Should be "rockchip,iommu"
   10 - reg             : Address space for the configuration registers
   11 - interrupts      : Interrupt specifier for the IOMMU instance
   12 - interrupt-names : Interrupt name for the IOMMU instance
   13 - #iommu-cells    : Should be <0>.  This indicates the iommu is a
   14                     "single-master" device, and needs no additional information
   15                     to associate with its master device.  See:
   16                     Documentation/devicetree/bindings/iommu/iommu.txt
   17 - clocks          : A list of clocks required for the IOMMU to be accessible by
   18                     the host CPU.
   19 - clock-names     : Should contain the following:
   20         "iface" - Main peripheral bus clock (PCLK/HCL) (required)
   21         "aclk"  - AXI bus clock (required)
   22 
   23 Optional properties:
   24 - rockchip,disable-mmu-reset : Don't use the mmu reset operation.
   25                                Some mmu instances may produce unexpected results
   26                                when the reset operation is used.
   27 
   28 Example:
   29 
   30         vopl_mmu: iommu@ff940300 {
   31                 compatible = "rockchip,iommu";
   32                 reg = <0xff940300 0x100>;
   33                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
   34                 interrupt-names = "vopl_mmu";
   35                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
   36                 clock-names = "aclk", "iface";
   37                 #iommu-cells = <0>;
   38         };
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