ti,omap-iommu.txt

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    1 OMAP2+ IOMMU
    2 
    3 Required properties:
    4 - compatible : Should be one of,
    5                 "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances
    6                 "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances
    7                 "ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances
    8                 "ti,dra7-iommu" for DRA7xx IOMMU instances
    9 - ti,hwmods  : Name of the hwmod associated with the IOMMU instance
   10 - reg        : Address space for the configuration registers
   11 - interrupts : Interrupt specifier for the IOMMU instance
   12 - #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices,
   13                  and needs no additional data in the pargs specifier. Please
   14                  also refer to the generic bindings document for more info
   15                  on this property,
   16                      Documentation/devicetree/bindings/iommu/iommu.txt
   17 
   18 Optional properties:
   19 - ti,#tlb-entries : Number of entries in the translation look-aside buffer.
   20                     Should be either 8 or 32 (default: 32)
   21 - ti,iommu-bus-err-back : Indicates the IOMMU instance supports throwing
   22                           back a bus error response on MMU faults.
   23 - ti,syscon-mmuconfig : Should be a pair of the phandle to the DSP_SYSTEM
   24                         syscon node that contains the additional control
   25                         register for enabling the MMU, and the MMU instance
   26                         number (0-indexed) within the sub-system. This property
   27                         is required for DSP IOMMU instances on DRA7xx SoCs. The
   28                         instance number should be 0 for DSP MDMA MMUs and 1 for
   29                         DSP EDMA MMUs.
   30 
   31 Example:
   32         /* OMAP3 ISP MMU */
   33         mmu_isp: mmu@480bd400 {
   34                 #iommu-cells = <0>;
   35                 compatible = "ti,omap2-iommu";
   36                 reg = <0x480bd400 0x80>;
   37                 interrupts = <24>;
   38                 ti,hwmods = "mmu_isp";
   39                 ti,#tlb-entries = <8>;
   40         };
   41 
   42         /* DRA74x DSP2 MMUs */
   43         mmu0_dsp2: mmu@41501000 {
   44                 compatible = "ti,dra7-dsp-iommu";
   45                 reg = <0x41501000 0x100>;
   46                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
   47                 ti,hwmods = "mmu0_dsp2";
   48                 #iommu-cells = <0>;
   49                 ti,syscon-mmuconfig = <&dsp2_system 0x0>;
   50         };
   51 
   52         mmu1_dsp2: mmu@41502000 {
   53                 compatible = "ti,dra7-dsp-iommu";
   54                 reg = <0x41502000 0x100>;
   55                 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
   56                 ti,hwmods = "mmu1_dsp2";
   57                 #iommu-cells = <0>;
   58                 ti,syscon-mmuconfig = <&dsp2_system 0x1>;
   59         };

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