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     1 Chips&Media Coda multi-standard codec IP
    2 ========================================
    3 
    4 Coda codec IPs are present in i.MX SoCs in various versions,
    5 called VPU (Video Processing Unit).
    6 
    7 Required properties:
    8 - compatible : should be "fsl,<chip>-src" for i.MX SoCs:
    9   (a) "fsl,imx27-vpu" for CodaDx6 present in i.MX27
   10   (b) "fsl,imx51-vpu" for CodaHx4 present in i.MX51
   11   (c) "fsl,imx53-vpu" for CODA7541 present in i.MX53
   12   (d) "fsl,imx6q-vpu" for CODA960 present in i.MX6q
   13 - reg: should be register base and length as documented in the
   14   SoC reference manual
   15 - interrupts : Should contain the VPU interrupt. For CODA960,
   16   a second interrupt is needed for the MJPEG unit.
   17 - clocks : Should contain the ahb and per clocks, in the order
   18   determined by the clock-names property.
   19 - clock-names : Should be "ahb", "per"
   20 - iram : phandle pointing to the SRAM device node
   21 
   22 Example:
   23 
   24 vpu: vpu@63ff4000 {
   25         compatible = "fsl,imx53-vpu";
   26         reg = <0x63ff4000 0x1000>;
   27         interrupts = <9>;
   28         clocks = <&clks 63>, <&clks 63>;
   29         clock-names = "ahb", "per";
   30         iram = <&ocram>;
   31 };
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