mediatek,vcodec-encoder.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 
    3 %YAML 1.2
    4 ---
    5 $id: http://devicetree.org/schemas/media/mediatek,vcodec-encoder.yaml#
    6 $schema: http://devicetree.org/meta-schemas/core.yaml#
    7 
    8 title: Mediatek Video Encode Accelerator
    9 
   10 maintainers:
   11   - Yunfei Dong <yunfei.dong@mediatek.com>
   12 
   13 description: |+
   14   Mediatek Video Encode is the video encode hardware present in Mediatek
   15   SoCs which supports high resolution encoding functionalities.
   16 
   17 properties:
   18   compatible:
   19     enum:
   20       - mediatek,mt8173-vcodec-enc-vp8
   21       - mediatek,mt8173-vcodec-enc
   22       - mediatek,mt8183-vcodec-enc
   23       - mediatek,mt8192-vcodec-enc
   24       - mediatek,mt8195-vcodec-enc
   25 
   26   reg:
   27     maxItems: 1
   28 
   29   interrupts:
   30     maxItems: 1
   31 
   32   clocks:
   33     minItems: 1
   34     maxItems: 5
   35 
   36   clock-names:
   37     minItems: 1
   38     maxItems: 5
   39 
   40   assigned-clocks: true
   41 
   42   assigned-clock-parents: true
   43 
   44   iommus:
   45     minItems: 1
   46     maxItems: 32
   47     description: |
   48       List of the hardware port in respective IOMMU block for current Socs.
   49       Refer to bindings/iommu/mediatek,iommu.yaml.
   50 
   51   dma-ranges:
   52     maxItems: 1
   53     description: |
   54       Describes the physical address space of IOMMU maps to memory.
   55 
   56   mediatek,vpu:
   57     $ref: /schemas/types.yaml#/definitions/phandle
   58     description:
   59       Describes point to vpu.
   60 
   61   mediatek,scp:
   62     $ref: /schemas/types.yaml#/definitions/phandle
   63     description:
   64       Describes point to scp.
   65 
   66   power-domains:
   67     maxItems: 1
   68 
   69 required:
   70   - compatible
   71   - reg
   72   - interrupts
   73   - clocks
   74   - clock-names
   75   - iommus
   76   - assigned-clocks
   77   - assigned-clock-parents
   78 
   79 allOf:
   80   - if:
   81       properties:
   82         compatible:
   83           contains:
   84             enum:
   85               - mediatek,mt8183-vcodec-enc
   86               - mediatek,mt8192-vcodec-enc
   87 
   88     then:
   89       required:
   90         - mediatek,scp
   91 
   92   - if:
   93       properties:
   94         compatible:
   95           contains:
   96             enum:
   97               - mediatek,mt8173-vcodec-enc-vp8
   98               - mediatek,mt8173-vcodec-enc
   99 
  100     then:
  101       required:
  102         - mediatek,vpu
  103 
  104   - if:
  105       properties:
  106         compatible:
  107           enum:
  108             - mediatek,mt8173-vcodec-enc
  109             - mediatek,mt8192-vcodec-enc
  110 
  111     then:
  112       properties:
  113         clock:
  114           items:
  115             minItems: 1
  116             maxItems: 1
  117         clock-names:
  118           items:
  119             - const: venc_sel
  120     else:  # for vp8 hw decoder
  121       properties:
  122         clock:
  123           items:
  124             minItems: 1
  125             maxItems: 1
  126         clock-names:
  127           items:
  128             - const: venc_lt_sel
  129 
  130 additionalProperties: false
  131 
  132 examples:
  133   - |
  134     #include <dt-bindings/interrupt-controller/arm-gic.h>
  135     #include <dt-bindings/clock/mt8173-clk.h>
  136     #include <dt-bindings/memory/mt8173-larb-port.h>
  137     #include <dt-bindings/interrupt-controller/irq.h>
  138 
  139     vcodec_enc_avc: vcodec@18002000 {
  140       compatible = "mediatek,mt8173-vcodec-enc";
  141       reg = <0x18002000 0x1000>;
  142       interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
  143       iommus = <&iommu M4U_PORT_VENC_RCPU>,
  144              <&iommu M4U_PORT_VENC_REC>,
  145              <&iommu M4U_PORT_VENC_BSDMA>,
  146              <&iommu M4U_PORT_VENC_SV_COMV>,
  147              <&iommu M4U_PORT_VENC_RD_COMV>,
  148              <&iommu M4U_PORT_VENC_CUR_LUMA>,
  149              <&iommu M4U_PORT_VENC_CUR_CHROMA>,
  150              <&iommu M4U_PORT_VENC_REF_LUMA>,
  151              <&iommu M4U_PORT_VENC_REF_CHROMA>,
  152              <&iommu M4U_PORT_VENC_NBM_RDMA>,
  153              <&iommu M4U_PORT_VENC_NBM_WDMA>;
  154       mediatek,vpu = <&vpu>;
  155       clocks = <&topckgen CLK_TOP_VENC_SEL>;
  156       clock-names = "venc_sel";
  157       assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
  158       assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
  159     };
  160 
  161     vcodec_enc_vp8: vcodec@19002000 {
  162       compatible = "mediatek,mt8173-vcodec-enc-vp8";
  163       reg =  <0x19002000 0x1000>;       /* VENC_LT_SYS */
  164       interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
  165       iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
  166              <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
  167              <&iommu M4U_PORT_VENC_BSDMA_SET2>,
  168              <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
  169              <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
  170              <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
  171              <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
  172              <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
  173              <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
  174       mediatek,vpu = <&vpu>;
  175       clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
  176       clock-names = "venc_lt_sel";
  177       assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
  178       assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
  179     };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/media/mediatek,vcodec-encoder.yaml

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sys/contrib/device-tree/Bindings/media/mediatek,vcodec-encoder.yaml