mediatek,vcodec-subdev-decoder.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 
    3 %YAML 1.2
    4 ---
    5 $id: "http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#"
    6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
    7 
    8 title: Mediatek Video Decode Accelerator With Multi Hardware
    9 
   10 maintainers:
   11   - Yunfei Dong <yunfei.dong@mediatek.com>
   12 
   13 description: |
   14   Mediatek Video Decode is the video decode hardware present in Mediatek
   15   SoCs which supports high resolution decoding functionalities. Required
   16   parent and child device node.
   17 
   18   About the Decoder Hardware Block Diagram, please check below:
   19 
   20     +------------------------------------------------+-------------------------------------+
   21     |                                                |                                     |
   22     |  input -> lat soc HW -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output  |
   23     |            ||             ||                   |                     ||              |
   24     +------------||-------------||-------------------+---------------------||--------------+
   25                  ||     lat     ||                   |               core workqueue  <parent>
   26     -------------||-------------||-------------------|---------------------||---------------
   27                  ||<------------||----------------HW index---------------->||        <child>
   28                  \/             \/                                         \/
   29                +-------------------------------------------------------------+
   30                |                          enable/disable                     |
   31                |                 clk     power    irq    iommu               |
   32                |                   (lat/lat soc/core0/core1)                 |
   33                +-------------------------------------------------------------+
   34 
   35   As above, there are parent and child devices, child mean each hardware. The child device
   36   controls the information of each hardware independent which include clk/power/irq.
   37 
   38   There are two workqueues in parent device: lat workqueue and core workqueue. They are used
   39   to lat and core hardware deocder. Lat workqueue need to get input bitstream and lat buffer,
   40   then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode
   41   done. Core workqueue need to get lat buffer and output buffer, then enable core to decode,
   42   writing the result to output buffer, disable hardware when core decode done. These two
   43   hardwares will decode each frame cyclically.
   44 
   45   For the smi common may not the same for each hardware, can't combine all hardware in one node,
   46   or leading to iommu fault when access dram data.
   47 
   48   Lat soc is a hardware which is related with some larb(local arbiter) ports. For mt8195
   49   platform, there are some ports like RDMA, UFO in lat soc larb, need to enable its power and
   50   clock when lat start to work, don't have interrupt.
   51 
   52   mt8195: lat soc HW + lat HW + core HW
   53   mt8192: lat HW + core HW
   54 
   55 properties:
   56   compatible:
   57     enum:
   58       - mediatek,mt8192-vcodec-dec
   59       - mediatek,mt8186-vcodec-dec
   60       - mediatek,mt8195-vcodec-dec
   61 
   62   reg:
   63     maxItems: 1
   64 
   65   iommus:
   66     minItems: 1
   67     maxItems: 32
   68     description: |
   69       List of the hardware port in respective IOMMU block for current Socs.
   70       Refer to bindings/iommu/mediatek,iommu.yaml.
   71 
   72   mediatek,scp:
   73     $ref: /schemas/types.yaml#/definitions/phandle
   74     description: |
   75       The node of system control processor (SCP), using
   76       the remoteproc & rpmsg framework.
   77 
   78   dma-ranges:
   79     maxItems: 1
   80     description: |
   81       Describes the physical address space of IOMMU maps to memory.
   82 
   83   "#address-cells":
   84     const: 2
   85 
   86   "#size-cells":
   87     const: 2
   88 
   89   ranges: true
   90 
   91 # Required child node:
   92 patternProperties:
   93   '^vcodec-lat@[0-9a-f]+$':
   94     type: object
   95 
   96     properties:
   97       compatible:
   98         enum:
   99           - mediatek,mtk-vcodec-lat
  100           - mediatek,mtk-vcodec-lat-soc
  101 
  102       reg:
  103         maxItems: 1
  104 
  105       interrupts:
  106         maxItems: 1
  107 
  108       iommus:
  109         minItems: 1
  110         maxItems: 32
  111         description: |
  112           List of the hardware port in respective IOMMU block for current Socs.
  113           Refer to bindings/iommu/mediatek,iommu.yaml.
  114 
  115       clocks:
  116         maxItems: 5
  117 
  118       clock-names:
  119         items:
  120           - const: sel
  121           - const: soc-vdec
  122           - const: soc-lat
  123           - const: vdec
  124           - const: top
  125 
  126       assigned-clocks:
  127         maxItems: 1
  128 
  129       assigned-clock-parents:
  130         maxItems: 1
  131 
  132       power-domains:
  133         maxItems: 1
  134 
  135     required:
  136       - compatible
  137       - reg
  138       - iommus
  139       - clocks
  140       - clock-names
  141       - assigned-clocks
  142       - assigned-clock-parents
  143       - power-domains
  144 
  145     additionalProperties: false
  146 
  147   '^vcodec-core@[0-9a-f]+$':
  148     type: object
  149 
  150     properties:
  151       compatible:
  152         const: mediatek,mtk-vcodec-core
  153 
  154       reg:
  155         maxItems: 1
  156 
  157       interrupts:
  158         maxItems: 1
  159 
  160       iommus:
  161         minItems: 1
  162         maxItems: 32
  163         description: |
  164           List of the hardware port in respective IOMMU block for current Socs.
  165           Refer to bindings/iommu/mediatek,iommu.yaml.
  166 
  167       clocks:
  168         maxItems: 5
  169 
  170       clock-names:
  171         items:
  172           - const: sel
  173           - const: soc-vdec
  174           - const: soc-lat
  175           - const: vdec
  176           - const: top
  177 
  178       assigned-clocks:
  179         maxItems: 1
  180 
  181       assigned-clock-parents:
  182         maxItems: 1
  183 
  184       power-domains:
  185         maxItems: 1
  186 
  187     required:
  188       - compatible
  189       - reg
  190       - interrupts
  191       - iommus
  192       - clocks
  193       - clock-names
  194       - assigned-clocks
  195       - assigned-clock-parents
  196       - power-domains
  197 
  198     additionalProperties: false
  199 
  200 required:
  201   - compatible
  202   - reg
  203   - iommus
  204   - mediatek,scp
  205   - dma-ranges
  206   - ranges
  207 
  208 if:
  209   properties:
  210     compatible:
  211       contains:
  212         enum:
  213           - mediatek,mtk-vcodec-lat
  214 
  215 then:
  216   required:
  217     - interrupts
  218 
  219 additionalProperties: false
  220 
  221 examples:
  222   - |
  223     #include <dt-bindings/interrupt-controller/arm-gic.h>
  224     #include <dt-bindings/memory/mt8192-larb-port.h>
  225     #include <dt-bindings/interrupt-controller/irq.h>
  226     #include <dt-bindings/clock/mt8192-clk.h>
  227     #include <dt-bindings/power/mt8192-power.h>
  228 
  229     bus@16000000 {
  230         #address-cells = <2>;
  231         #size-cells = <2>;
  232         ranges = <0 0x16000000 0x16000000 0 0x40000>;
  233 
  234         video-codec@16000000 {
  235             compatible = "mediatek,mt8192-vcodec-dec";
  236             mediatek,scp = <&scp>;
  237             iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
  238             dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
  239             #address-cells = <2>;
  240             #size-cells = <2>;
  241             ranges = <0 0 0 0x16000000 0 0x40000>;
  242             reg = <0 0x16000000 0 0x1000>;              /* VDEC_SYS */
  243             vcodec-lat@10000 {
  244                 compatible = "mediatek,mtk-vcodec-lat";
  245                 reg = <0 0x10000 0 0x800>;
  246                 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
  247                 iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
  248                     <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
  249                     <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
  250                     <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
  251                     <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
  252                     <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
  253                     <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
  254                     <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
  255                 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
  256                     <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
  257                     <&vdecsys_soc CLK_VDEC_SOC_LAT>,
  258                     <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
  259                     <&topckgen CLK_TOP_MAINPLL_D4>;
  260                 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
  261                 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
  262                 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
  263                 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
  264             };
  265 
  266             vcodec-core@25000 {
  267                 compatible = "mediatek,mtk-vcodec-core";
  268                 reg = <0 0x25000 0 0x1000>;
  269                 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
  270                 iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
  271                     <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
  272                     <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
  273                     <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
  274                     <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
  275                     <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
  276                     <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
  277                     <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
  278                     <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
  279                     <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
  280                     <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
  281                 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
  282                     <&vdecsys CLK_VDEC_VDEC>,
  283                     <&vdecsys CLK_VDEC_LAT>,
  284                     <&vdecsys CLK_VDEC_LARB1>,
  285                     <&topckgen CLK_TOP_MAINPLL_D4>;
  286                 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
  287                 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
  288                 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
  289                 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
  290             };
  291         };
  292     };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/media/mediatek,vcodec-subdev-decoder.yaml

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sys/contrib/device-tree/Bindings/media/mediatek,vcodec-subdev-decoder.yaml