nxp,imx-mipi-csi2.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
    8 
    9 maintainers:
   10   - Rui Miguel Silva <rmfrfs@gmail.com>
   11   - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
   12 
   13 description: |-
   14   The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
   15   receiver IP core named CSIS. The IP core originates from Samsung, and may be
   16   compatible with some of the Exynos4 and S5P SoCs. i.MX7 SoCs use CSIS version
   17   3.3, and i.MX8 SoCs use CSIS version 3.6.3.
   18 
   19   While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
   20   completely wrapped by the CSIS and doesn't expose a control interface of its
   21   own. This binding thus covers both IP cores.
   22 
   23 properties:
   24   compatible:
   25     oneOf:
   26       - enum:
   27           - fsl,imx7-mipi-csi2
   28           - fsl,imx8mm-mipi-csi2
   29       - items:
   30           - enum:
   31               - fsl,imx8mp-mipi-csi2
   32           - const: fsl,imx8mm-mipi-csi2
   33 
   34   reg:
   35     maxItems: 1
   36 
   37   interrupts:
   38     maxItems: 1
   39 
   40   clocks:
   41     minItems: 3
   42     items:
   43       - description: The peripheral clock (a.k.a. APB clock)
   44       - description: The external clock (optionally used as the pixel clock)
   45       - description: The MIPI D-PHY clock
   46       - description: The AXI clock
   47 
   48   clock-names:
   49     minItems: 3
   50     items:
   51       - const: pclk
   52       - const: wrap
   53       - const: phy
   54       - const: axi
   55 
   56   power-domains:
   57     maxItems: 1
   58 
   59   phy-supply:
   60     description: The MIPI D-PHY digital power supply
   61 
   62   resets:
   63     items:
   64       - description: MIPI D-PHY slave reset
   65 
   66   clock-frequency:
   67     description: The desired external clock ("wrap") frequency, in Hz
   68     default: 166000000
   69 
   70   ports:
   71     $ref: /schemas/graph.yaml#/properties/ports
   72 
   73     properties:
   74       port@0:
   75         $ref: /schemas/graph.yaml#/$defs/port-base
   76         unevaluatedProperties: false
   77         description:
   78           Input port node, single endpoint describing the CSI-2 transmitter.
   79 
   80         properties:
   81           endpoint:
   82             $ref: video-interfaces.yaml#
   83             unevaluatedProperties: false
   84 
   85             properties:
   86               data-lanes:
   87                 description:
   88                   Note that 'fsl,imx7-mipi-csi2' only supports up to 2 data lines.
   89                 minItems: 1
   90                 items:
   91                   - const: 1
   92                   - const: 2
   93                   - const: 3
   94                   - const: 4
   95 
   96             required:
   97               - data-lanes
   98 
   99       port@1:
  100         $ref: /schemas/graph.yaml#/properties/port
  101         description:
  102           Output port node
  103 
  104 required:
  105   - compatible
  106   - reg
  107   - interrupts
  108   - clocks
  109   - clock-names
  110   - power-domains
  111   - ports
  112 
  113 additionalProperties: false
  114 
  115 allOf:
  116   - if:
  117       properties:
  118         compatible:
  119           contains:
  120             const: fsl,imx7-mipi-csi2
  121     then:
  122       required:
  123         - phy-supply
  124         - resets
  125     else:
  126       properties:
  127         clocks:
  128           minItems: 4
  129         clock-names:
  130           minItems: 4
  131         phy-supply: false
  132         resets: false
  133 
  134 examples:
  135   - |
  136     #include <dt-bindings/clock/imx7d-clock.h>
  137     #include <dt-bindings/interrupt-controller/arm-gic.h>
  138     #include <dt-bindings/interrupt-controller/irq.h>
  139     #include <dt-bindings/reset/imx7-reset.h>
  140 
  141     mipi-csi@30750000 {
  142         compatible = "fsl,imx7-mipi-csi2";
  143         reg = <0x30750000 0x10000>;
  144         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  145 
  146         clocks = <&clks IMX7D_IPG_ROOT_CLK>,
  147                  <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
  148                  <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
  149         clock-names = "pclk", "wrap", "phy";
  150         clock-frequency = <166000000>;
  151 
  152         power-domains = <&pgc_mipi_phy>;
  153         phy-supply = <&reg_1p0d>;
  154         resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
  155 
  156         ports {
  157             #address-cells = <1>;
  158             #size-cells = <0>;
  159 
  160             port@0 {
  161                 reg = <0>;
  162 
  163                 mipi_from_sensor: endpoint {
  164                     remote-endpoint = <&ov2680_to_mipi>;
  165                     data-lanes = <1>;
  166                 };
  167             };
  168 
  169             port@1 {
  170                 reg = <1>;
  171 
  172                 mipi_vc0_to_csi_mux: endpoint {
  173                     remote-endpoint = <&csi_mux_from_mipi_vc0>;
  174                 };
  175             };
  176         };
  177     };
  178 
  179   - |
  180     #include <dt-bindings/clock/imx8mm-clock.h>
  181     #include <dt-bindings/interrupt-controller/arm-gic.h>
  182     #include <dt-bindings/interrupt-controller/irq.h>
  183 
  184     mipi-csi@32e30000 {
  185         compatible = "fsl,imx8mm-mipi-csi2";
  186         reg = <0x32e30000 0x1000>;
  187         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  188         clock-frequency = <333000000>;
  189         clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
  190                  <&clk IMX8MM_CLK_CSI1_ROOT>,
  191                  <&clk IMX8MM_CLK_CSI1_PHY_REF>,
  192                  <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
  193         clock-names = "pclk", "wrap", "phy", "axi";
  194         power-domains = <&mipi_pd>;
  195 
  196         ports {
  197             #address-cells = <1>;
  198             #size-cells = <0>;
  199 
  200             port@0 {
  201                 reg = <0>;
  202 
  203                 imx8mm_mipi_csi_in: endpoint {
  204                     remote-endpoint = <&imx477_out>;
  205                     data-lanes = <1 2 3 4>;
  206                 };
  207             };
  208 
  209             port@1 {
  210                 reg = <1>;
  211 
  212                 imx8mm_mipi_csi_out: endpoint {
  213                     remote-endpoint = <&csi_in>;
  214                 };
  215             };
  216         };
  217     };
  218 
  219 ...

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