renesas,drif.yaml

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    1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/media/renesas,drif.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Renesas R-Car Gen3 Digital Radio Interface Controller (DRIF)
    8 
    9 maintainers:
   10   - Ramesh Shanmugasundaram <rashanmu@gmail.com>
   11   - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
   12 
   13 description: |
   14   R-Car Gen3 DRIF is a SPI like receive only slave device. A general
   15   representation of DRIF interfacing with a master device is shown below.
   16 
   17   +---------------------+                +---------------------+
   18   |                     |-----SCK------->|CLK                  |
   19   |       Master        |-----SS-------->|SYNC  DRIFn (slave)  |
   20   |                     |-----SD0------->|D0                   |
   21   |                     |-----SD1------->|D1                   |
   22   +---------------------+                +---------------------+
   23 
   24   As per datasheet, each DRIF channel (drifn) is made up of two internal
   25   channels (drifn0 & drifn1). These two internal channels share the common
   26   CLK & SYNC. Each internal channel has its own dedicated resources like
   27   irq, dma channels, address space & clock. This internal split is not
   28   visible to the external master device.
   29 
   30   The device tree model represents each internal channel as a separate node.
   31   The internal channels sharing the CLK & SYNC are tied together by their
   32   phandles using a property called "renesas,bonding". For the rest of
   33   the documentation, unless explicitly stated, the word channel implies an
   34   internal channel.
   35 
   36   When both internal channels are enabled they need to be managed together
   37   as one (i.e.) they cannot operate alone as independent devices. Out of the
   38   two, one of them needs to act as a primary device that accepts common
   39   properties of both the internal channels. This channel is identified by a
   40   property called "renesas,primary-bond".
   41 
   42   To summarize,
   43      * When both the internal channels that are bonded together are enabled,
   44        the zeroth channel is selected as primary-bond. This channels accepts
   45        properties common to all the members of the bond.
   46      * When only one of the bonded channels need to be enabled, the property
   47        "renesas,bonding" or "renesas,primary-bond" will have no effect. That
   48        enabled channel can act alone as any other independent device.
   49 
   50 properties:
   51   compatible:
   52     items:
   53       - enum:
   54           - renesas,r8a7795-drif        # R-Car H3
   55           - renesas,r8a7796-drif        # R-Car M3-W
   56           - renesas,r8a77965-drif       # R-Car M3-N
   57           - renesas,r8a77990-drif       # R-Car E3
   58       - const: renesas,rcar-gen3-drif   # Generic R-Car Gen3 compatible device
   59 
   60   reg:
   61     maxItems: 1
   62 
   63   interrupts:
   64     maxItems: 1
   65 
   66   clocks:
   67     maxItems: 1
   68 
   69   clock-names:
   70     const: fck
   71 
   72   resets:
   73     maxItems: 1
   74 
   75   dmas:
   76     minItems: 1
   77     maxItems: 2
   78 
   79   dma-names:
   80     minItems: 1
   81     items:
   82       - const: rx
   83       - const: rx
   84 
   85   renesas,bonding:
   86     $ref: /schemas/types.yaml#/definitions/phandle
   87     description:
   88       The phandle to the other internal channel of DRIF
   89 
   90   power-domains:
   91     maxItems: 1
   92 
   93   renesas,primary-bond:
   94     type: boolean
   95     description:
   96       Indicates that the channel acts as primary among the bonded channels.
   97 
   98   port:
   99     $ref: /schemas/graph.yaml#/$defs/port-base
  100     unevaluatedProperties: false
  101     description:
  102       Child port node corresponding to the data input. The port node must
  103       contain at least one endpoint.
  104 
  105     properties:
  106       endpoint:
  107         $ref: /schemas/graph.yaml#/$defs/endpoint-base
  108         unevaluatedProperties: false
  109 
  110         properties:
  111           sync-active:
  112             $ref: /schemas/types.yaml#/definitions/uint32
  113             enum: [0, 1]
  114             description:
  115               Indicates sync signal polarity, 0/1 for low/high respectively.
  116               This property maps to SYNCAC bit in the hardware manual. The
  117               default is 1 (active high).
  118 
  119 required:
  120   - compatible
  121   - reg
  122   - interrupts
  123   - clocks
  124   - clock-names
  125   - resets
  126   - dmas
  127   - dma-names
  128   - renesas,bonding
  129   - power-domains
  130 
  131 allOf:
  132   - if:
  133       required:
  134         - renesas,primary-bond
  135     then:
  136       required:
  137         - pinctrl-0
  138         - pinctrl-names
  139         - port
  140 
  141   - if:
  142       required:
  143         - port
  144     then:
  145       required:
  146         - pinctrl-0
  147         - pinctrl-names
  148     else:
  149       properties:
  150         pinctrl-0: false
  151         pinctrl-names: false
  152 
  153 additionalProperties: false
  154 
  155 examples:
  156   # Example with both internal channels enabled.
  157   #
  158   # When interfacing with a third party tuner device with two data pins as shown
  159   # below.
  160   #
  161   # +---------------------+                +---------------------+
  162   # |                     |-----SCK------->|CLK                  |
  163   # |       Master        |-----SS-------->|SYNC  DRIFn (slave)  |
  164   # |                     |-----SD0------->|D0                   |
  165   # |                     |-----SD1------->|D1                   |
  166   # +---------------------+                +---------------------+
  167   - |
  168     #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
  169     #include <dt-bindings/interrupt-controller/arm-gic.h>
  170     #include <dt-bindings/power/r8a7795-sysc.h>
  171 
  172     soc {
  173             #address-cells = <2>;
  174             #size-cells = <2>;
  175 
  176             drif00: rif@e6f40000 {
  177                     compatible = "renesas,r8a7795-drif",
  178                                  "renesas,rcar-gen3-drif";
  179                     reg = <0 0xe6f40000 0 0x64>;
  180                     interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
  181                     clocks = <&cpg CPG_MOD 515>;
  182                     clock-names = "fck";
  183                     dmas = <&dmac1 0x20>, <&dmac2 0x20>;
  184                     dma-names = "rx", "rx";
  185                     power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
  186                     renesas,bonding = <&drif01>;
  187                     resets = <&cpg 515>;
  188                     renesas,primary-bond;
  189                     pinctrl-0 = <&drif0_pins>;
  190                     pinctrl-names = "default";
  191                     port {
  192                             drif0_ep: endpoint {
  193                                  remote-endpoint = <&tuner_ep>;
  194                             };
  195                     };
  196             };
  197 
  198             drif01: rif@e6f50000 {
  199                     compatible = "renesas,r8a7795-drif",
  200                                  "renesas,rcar-gen3-drif";
  201                     reg = <0 0xe6f50000 0 0x64>;
  202                     interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
  203                     clocks = <&cpg CPG_MOD 514>;
  204                     clock-names = "fck";
  205                     dmas = <&dmac1 0x22>, <&dmac2 0x22>;
  206                     dma-names = "rx", "rx";
  207                     power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
  208                     renesas,bonding = <&drif00>;
  209                     resets = <&cpg 514>;
  210             };
  211     };
  212 
  213   # Example with internal channel 1 alone enabled.
  214   #
  215   # When interfacing with a third party tuner device with one data pin as shown
  216   # below.
  217   #
  218   # +---------------------+                +---------------------+
  219   # |                     |-----SCK------->|CLK                  |
  220   # |       Master        |-----SS-------->|SYNC  DRIFn (slave)  |
  221   # |                     |                |D0 (unused)          |
  222   # |                     |-----SD-------->|D1                   |
  223   # +---------------------+                +---------------------+
  224   - |
  225     #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
  226     #include <dt-bindings/interrupt-controller/arm-gic.h>
  227     #include <dt-bindings/power/r8a7795-sysc.h>
  228 
  229     soc {
  230             #address-cells = <2>;
  231             #size-cells = <2>;
  232 
  233             drif10: rif@e6f60000 {
  234                     compatible = "renesas,r8a7795-drif",
  235                                  "renesas,rcar-gen3-drif";
  236                     reg = <0 0xe6f60000 0 0x64>;
  237                     interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
  238                     clocks = <&cpg CPG_MOD 513>;
  239                     clock-names = "fck";
  240                     dmas = <&dmac1 0x24>, <&dmac2 0x24>;
  241                     dma-names = "rx", "rx";
  242                     power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
  243                     resets = <&cpg 513>;
  244                     renesas,bonding = <&drif11>;
  245             };
  246 
  247             drif11: rif@e6f70000 {
  248                     compatible = "renesas,r8a7795-drif",
  249                                  "renesas,rcar-gen3-drif";
  250                     reg = <0 0xe6f70000 0 0x64>;
  251                     interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
  252                     clocks = <&cpg CPG_MOD 512>;
  253                     clock-names = "fck";
  254                     dmas = <&dmac1 0x26>, <&dmac2 0x26>;
  255                     dma-names = "rx", "rx";
  256                     power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
  257                     resets = <&cpg 512>;
  258                     renesas,bonding = <&drif10>;
  259                     pinctrl-0 = <&drif1_pins>;
  260                     pinctrl-names = "default";
  261                     port {
  262                             drif1_ep: endpoint {
  263                                  remote-endpoint = <&tuner_ep1>;
  264                                  sync-active = <0>;
  265                             };
  266                     };
  267             };
  268     };
  269 ...

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/media/renesas,drif.yaml

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sys/contrib/device-tree/Bindings/media/renesas,drif.yaml