arm,pl353-smc.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl353-smc.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: ARM PL353 Static Memory Controller (SMC) device-tree bindings
    8 
    9 maintainers:
   10   - Miquel Raynal <miquel.raynal@bootlin.com>
   11   - Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
   12 
   13 description:
   14   The PL353 Static Memory Controller is a bus where you can connect two kinds
   15   of memory interfaces, which are NAND and memory mapped interfaces (such as
   16   SRAM or NOR).
   17 
   18 # We need a select here so we don't match all nodes with 'arm,primecell'
   19 select:
   20   properties:
   21     compatible:
   22       contains:
   23         const: arm,pl353-smc-r2p1
   24   required:
   25     - compatible
   26 
   27 properties:
   28   $nodename:
   29     pattern: "^memory-controller@[0-9a-f]+$"
   30 
   31   compatible:
   32     items:
   33       - const: arm,pl353-smc-r2p1
   34       - const: arm,primecell
   35 
   36   "#address-cells":
   37     const: 2
   38 
   39   "#size-cells":
   40     const: 1
   41 
   42   reg:
   43     items:
   44       - description:
   45           Configuration registers for the host and sub-controllers.
   46           The three chip select regions are defined in 'ranges'.
   47 
   48   clocks:
   49     items:
   50       - description: clock for the memory device bus
   51       - description: main clock of the SMC
   52 
   53   clock-names:
   54     items:
   55       - const: memclk
   56       - const: apb_pclk
   57 
   58   ranges:
   59     minItems: 1
   60     description: |
   61       Memory bus areas for interacting with the devices. Reflects
   62       the memory layout with four integer values following:
   63       <cs-number> 0 <offset> <size>
   64     items:
   65       - description: NAND bank 0
   66       - description: NOR/SRAM bank 0
   67       - description: NOR/SRAM bank 1
   68 
   69   interrupts: true
   70 
   71 patternProperties:
   72   "@[0-3],[a-f0-9]+$":
   73     type: object
   74     description: |
   75       The child device node represents the controller connected to the SMC
   76       bus. The controller can be a NAND controller or a pair of any memory
   77       mapped controllers such as NOR and SRAM controllers.
   78 
   79     properties:
   80       compatible:
   81         description:
   82           Compatible of memory controller.
   83 
   84       reg:
   85         items:
   86           - items:
   87               - description: |
   88                   Chip-select ID, as in the parent range property.
   89                 minimum: 0
   90                 maximum: 2
   91               - description: |
   92                   Offset of the memory region requested by the device.
   93               - description: |
   94                   Length of the memory region requested by the device.
   95 
   96     required:
   97       - compatible
   98       - reg
   99 
  100 required:
  101   - compatible
  102   - reg
  103   - clock-names
  104   - clocks
  105   - "#address-cells"
  106   - "#size-cells"
  107   - ranges
  108 
  109 additionalProperties: false
  110 
  111 examples:
  112   - |
  113     smcc: memory-controller@e000e000 {
  114       compatible = "arm,pl353-smc-r2p1", "arm,primecell";
  115       reg = <0xe000e000 0x0001000>;
  116       clock-names = "memclk", "apb_pclk";
  117       clocks = <&clkc 11>, <&clkc 44>;
  118       ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
  119                 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
  120                 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
  121       #address-cells = <2>;
  122       #size-cells = <1>;
  123 
  124       nfc0: nand-controller@0,0 {
  125         compatible = "arm,pl353-nand-r2p1";
  126         reg = <0 0 0x1000000>;
  127         #address-cells = <1>;
  128         #size-cells = <0>;
  129       };
  130     };

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