1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (c) 2020 MediaTek Inc.
3 %YAML 1.2
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
7
8 title: SMI (Smart Multimedia Interface) Common
9
10 maintainers:
11 - Yong Wu <yong.wu@mediatek.com>
12
13 description: |
14 The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
15
16 MediaTek SMI have two generations of HW architecture, here is the list
17 which generation the SoCs use:
18 generation 1: mt2701 and mt7623.
19 generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8192 and mt8195.
20
21 There's slight differences between the two SMI, for generation 2, the
22 register which control the iommu port is at each larb's register base. But
23 for generation 1, the register is at smi ao base(smi always on register
24 base). Besides that, the smi async clock should be prepared and enabled for
25 SMI generation 1 to transform the smi clock into emi clock domain, but that is
26 not needed for SMI generation 2.
27
28 properties:
29 compatible:
30 oneOf:
31 - enum:
32 - mediatek,mt2701-smi-common
33 - mediatek,mt2712-smi-common
34 - mediatek,mt6779-smi-common
35 - mediatek,mt6795-smi-common
36 - mediatek,mt8167-smi-common
37 - mediatek,mt8173-smi-common
38 - mediatek,mt8183-smi-common
39 - mediatek,mt8186-smi-common
40 - mediatek,mt8192-smi-common
41 - mediatek,mt8195-smi-common-vdo
42 - mediatek,mt8195-smi-common-vpp
43 - mediatek,mt8195-smi-sub-common
44
45 - description: for mt7623
46 items:
47 - const: mediatek,mt7623-smi-common
48 - const: mediatek,mt2701-smi-common
49
50 reg:
51 maxItems: 1
52
53 power-domains:
54 maxItems: 1
55
56 clocks:
57 description: |
58 apb and smi are mandatory. the async is only for generation 1 smi HW.
59 gals(global async local sync) also is optional, see below.
60 minItems: 2
61 items:
62 - description: apb is Advanced Peripheral Bus clock, It's the clock for
63 setting the register.
64 - description: smi is the clock for transfer data and command.
65 - description: Either asynchronous clock to help transform the smi clock
66 into the emi clock domain on Gen1 h/w, or the path0 clock of gals.
67 - description: gals1 is the path1 clock of gals.
68
69 clock-names:
70 minItems: 2
71 maxItems: 4
72
73 mediatek,smi:
74 $ref: /schemas/types.yaml#/definitions/phandle
75 description: a phandle to the smi-common node above. Only for sub-common.
76
77 required:
78 - compatible
79 - reg
80 - power-domains
81 - clocks
82 - clock-names
83
84 allOf:
85 - if: # only for gen1 HW
86 properties:
87 compatible:
88 contains:
89 enum:
90 - mediatek,mt2701-smi-common
91 then:
92 properties:
93 clocks:
94 minItems: 3
95 maxItems: 3
96 clock-names:
97 items:
98 - const: apb
99 - const: smi
100 - const: async
101
102 - if: # only for sub common
103 properties:
104 compatible:
105 contains:
106 enum:
107 - mediatek,mt8195-smi-sub-common
108 then:
109 required:
110 - mediatek,smi
111 properties:
112 clocks:
113 minItems: 3
114 maxItems: 3
115 clock-names:
116 items:
117 - const: apb
118 - const: smi
119 - const: gals0
120 else:
121 properties:
122 mediatek,smi: false
123
124 - if: # for gen2 HW that have gals
125 properties:
126 compatible:
127 enum:
128 - mediatek,mt6779-smi-common
129 - mediatek,mt8183-smi-common
130 - mediatek,mt8186-smi-common
131 - mediatek,mt8192-smi-common
132 - mediatek,mt8195-smi-common-vdo
133 - mediatek,mt8195-smi-common-vpp
134
135 then:
136 properties:
137 clocks:
138 minItems: 4
139 maxItems: 4
140 clock-names:
141 items:
142 - const: apb
143 - const: smi
144 - const: gals0
145 - const: gals1
146
147 else: # for gen2 HW that don't have gals
148 properties:
149 clocks:
150 minItems: 2
151 maxItems: 2
152 clock-names:
153 items:
154 - const: apb
155 - const: smi
156
157 additionalProperties: false
158
159 examples:
160 - |+
161 #include <dt-bindings/clock/mt8173-clk.h>
162 #include <dt-bindings/power/mt8173-power.h>
163
164 smi_common: smi@14022000 {
165 compatible = "mediatek,mt8173-smi-common";
166 reg = <0x14022000 0x1000>;
167 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
168 clocks = <&mmsys CLK_MM_SMI_COMMON>,
169 <&mmsys CLK_MM_SMI_COMMON>;
170 clock-names = "apb", "smi";
171 };
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