Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/memory-controllers/nvidia,tegra124-emc.yaml
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1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 %YAML 1.2 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 7 title: NVIDIA Tegra124 SoC External Memory Controller 8 9 maintainers: 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 13 description: | 14 The EMC interfaces with the off-chip SDRAM to service the request stream 15 sent from the memory controller. 16 17 properties: 18 compatible: 19 const: nvidia,tegra124-emc 20 21 reg: 22 maxItems: 1 23 24 clocks: 25 items: 26 - description: external memory clock 27 28 clock-names: 29 items: 30 - const: emc 31 32 "#interconnect-cells": 33 const: 0 34 35 nvidia,memory-controller: 36 $ref: /schemas/types.yaml#/definitions/phandle 37 description: 38 phandle of the memory controller node 39 40 power-domains: 41 maxItems: 1 42 description: 43 Phandle of the SoC "core" power domain. 44 45 operating-points-v2: 46 description: 47 Should contain freqs and voltages and opp-supported-hw property, which 48 is a bitfield indicating SoC speedo ID mask. 49 50 patternProperties: 51 "^emc-timings-[0-9]+$": 52 type: object 53 properties: 54 nvidia,ram-code: 55 $ref: /schemas/types.yaml#/definitions/uint32 56 description: 57 value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that 58 this timing set is used for 59 60 patternProperties: 61 "^timing-[0-9]+$": 62 type: object 63 properties: 64 clock-frequency: 65 description: 66 external memory clock rate in Hz 67 minimum: 1000000 68 maximum: 1000000000 69 70 nvidia,emc-auto-cal-config: 71 $ref: /schemas/types.yaml#/definitions/uint32 72 description: 73 value of the EMC_AUTO_CAL_CONFIG register for this set of 74 timings 75 76 nvidia,emc-auto-cal-config2: 77 $ref: /schemas/types.yaml#/definitions/uint32 78 description: 79 value of the EMC_AUTO_CAL_CONFIG2 register for this set of 80 timings 81 82 nvidia,emc-auto-cal-config3: 83 $ref: /schemas/types.yaml#/definitions/uint32 84 description: 85 value of the EMC_AUTO_CAL_CONFIG3 register for this set of 86 timings 87 88 nvidia,emc-auto-cal-interval: 89 description: 90 pad calibration interval in microseconds 91 $ref: /schemas/types.yaml#/definitions/uint32 92 minimum: 0 93 maximum: 2097151 94 95 nvidia,emc-bgbias-ctl0: 96 $ref: /schemas/types.yaml#/definitions/uint32 97 description: 98 value of the EMC_BGBIAS_CTL0 register for this set of timings 99 100 nvidia,emc-cfg: 101 $ref: /schemas/types.yaml#/definitions/uint32 102 description: 103 value of the EMC_CFG register for this set of timings 104 105 nvidia,emc-cfg-2: 106 $ref: /schemas/types.yaml#/definitions/uint32 107 description: 108 value of the EMC_CFG_2 register for this set of timings 109 110 nvidia,emc-ctt-term-ctrl: 111 $ref: /schemas/types.yaml#/definitions/uint32 112 description: 113 value of the EMC_CTT_TERM_CTRL register for this set of timings 114 115 nvidia,emc-mode-1: 116 $ref: /schemas/types.yaml#/definitions/uint32 117 description: 118 value of the EMC_MRW register for this set of timings 119 120 nvidia,emc-mode-2: 121 $ref: /schemas/types.yaml#/definitions/uint32 122 description: 123 value of the EMC_MRW2 register for this set of timings 124 125 nvidia,emc-mode-4: 126 $ref: /schemas/types.yaml#/definitions/uint32 127 description: 128 value of the EMC_MRW4 register for this set of timings 129 130 nvidia,emc-mode-reset: 131 $ref: /schemas/types.yaml#/definitions/uint32 132 description: 133 reset value of the EMC_MRS register for this set of timings 134 135 nvidia,emc-mrs-wait-cnt: 136 $ref: /schemas/types.yaml#/definitions/uint32 137 description: 138 value of the EMR_MRS_WAIT_CNT register for this set of timings 139 140 nvidia,emc-sel-dpd-ctrl: 141 $ref: /schemas/types.yaml#/definitions/uint32 142 description: 143 value of the EMC_SEL_DPD_CTRL register for this set of timings 144 145 nvidia,emc-xm2dqspadctrl2: 146 $ref: /schemas/types.yaml#/definitions/uint32 147 description: 148 value of the EMC_XM2DQSPADCTRL2 register for this set of timings 149 150 nvidia,emc-zcal-cnt-long: 151 description: 152 number of EMC clocks to wait before issuing any commands after 153 clock change 154 $ref: /schemas/types.yaml#/definitions/uint32 155 minimum: 0 156 maximum: 1023 157 158 nvidia,emc-zcal-interval: 159 $ref: /schemas/types.yaml#/definitions/uint32 160 description: 161 value of the EMC_ZCAL_INTERVAL register for this set of timings 162 163 nvidia,emc-configuration: 164 description: 165 EMC timing characterization data. These are the registers (see 166 section "15.6.2 EMC Registers" in the TRM) whose values need to 167 be specified, according to the board documentation. 168 $ref: /schemas/types.yaml#/definitions/uint32-array 169 items: 170 - description: EMC_RC 171 - description: EMC_RFC 172 - description: EMC_RFC_SLR 173 - description: EMC_RAS 174 - description: EMC_RP 175 - description: EMC_R2W 176 - description: EMC_W2R 177 - description: EMC_R2P 178 - description: EMC_W2P 179 - description: EMC_RD_RCD 180 - description: EMC_WR_RCD 181 - description: EMC_RRD 182 - description: EMC_REXT 183 - description: EMC_WEXT 184 - description: EMC_WDV 185 - description: EMC_WDV_MASK 186 - description: EMC_QUSE 187 - description: EMC_QUSE_WIDTH 188 - description: EMC_IBDLY 189 - description: EMC_EINPUT 190 - description: EMC_EINPUT_DURATION 191 - description: EMC_PUTERM_EXTRA 192 - description: EMC_PUTERM_WIDTH 193 - description: EMC_PUTERM_ADJ 194 - description: EMC_CDB_CNTL_1 195 - description: EMC_CDB_CNTL_2 196 - description: EMC_CDB_CNTL_3 197 - description: EMC_QRST 198 - description: EMC_QSAFE 199 - description: EMC_RDV 200 - description: EMC_RDV_MASK 201 - description: EMC_REFRESH 202 - description: EMC_BURST_REFRESH_NUM 203 - description: EMC_PRE_REFRESH_REQ_CNT 204 - description: EMC_PDEX2WR 205 - description: EMC_PDEX2RD 206 - description: EMC_PCHG2PDEN 207 - description: EMC_ACT2PDEN 208 - description: EMC_AR2PDEN 209 - description: EMC_RW2PDEN 210 - description: EMC_TXSR 211 - description: EMC_TXSRDLL 212 - description: EMC_TCKE 213 - description: EMC_TCKESR 214 - description: EMC_TPD 215 - description: EMC_TFAW 216 - description: EMC_TRPAB 217 - description: EMC_TCLKSTABLE 218 - description: EMC_TCLKSTOP 219 - description: EMC_TREFBW 220 - description: EMC_FBIO_CFG6 221 - description: EMC_ODT_WRITE 222 - description: EMC_ODT_READ 223 - description: EMC_FBIO_CFG5 224 - description: EMC_CFG_DIG_DLL 225 - description: EMC_CFG_DIG_DLL_PERIOD 226 - description: EMC_DLL_XFORM_DQS0 227 - description: EMC_DLL_XFORM_DQS1 228 - description: EMC_DLL_XFORM_DQS2 229 - description: EMC_DLL_XFORM_DQS3 230 - description: EMC_DLL_XFORM_DQS4 231 - description: EMC_DLL_XFORM_DQS5 232 - description: EMC_DLL_XFORM_DQS6 233 - description: EMC_DLL_XFORM_DQS7 234 - description: EMC_DLL_XFORM_DQS8 235 - description: EMC_DLL_XFORM_DQS9 236 - description: EMC_DLL_XFORM_DQS10 237 - description: EMC_DLL_XFORM_DQS11 238 - description: EMC_DLL_XFORM_DQS12 239 - description: EMC_DLL_XFORM_DQS13 240 - description: EMC_DLL_XFORM_DQS14 241 - description: EMC_DLL_XFORM_DQS15 242 - description: EMC_DLL_XFORM_QUSE0 243 - description: EMC_DLL_XFORM_QUSE1 244 - description: EMC_DLL_XFORM_QUSE2 245 - description: EMC_DLL_XFORM_QUSE3 246 - description: EMC_DLL_XFORM_QUSE4 247 - description: EMC_DLL_XFORM_QUSE5 248 - description: EMC_DLL_XFORM_QUSE6 249 - description: EMC_DLL_XFORM_QUSE7 250 - description: EMC_DLL_XFORM_ADDR0 251 - description: EMC_DLL_XFORM_ADDR1 252 - description: EMC_DLL_XFORM_ADDR2 253 - description: EMC_DLL_XFORM_ADDR3 254 - description: EMC_DLL_XFORM_ADDR4 255 - description: EMC_DLL_XFORM_ADDR5 256 - description: EMC_DLL_XFORM_QUSE8 257 - description: EMC_DLL_XFORM_QUSE9 258 - description: EMC_DLL_XFORM_QUSE10 259 - description: EMC_DLL_XFORM_QUSE11 260 - description: EMC_DLL_XFORM_QUSE12 261 - description: EMC_DLL_XFORM_QUSE13 262 - description: EMC_DLL_XFORM_QUSE14 263 - description: EMC_DLL_XFORM_QUSE15 264 - description: EMC_DLI_TRIM_TXDQS0 265 - description: EMC_DLI_TRIM_TXDQS1 266 - description: EMC_DLI_TRIM_TXDQS2 267 - description: EMC_DLI_TRIM_TXDQS3 268 - description: EMC_DLI_TRIM_TXDQS4 269 - description: EMC_DLI_TRIM_TXDQS5 270 - description: EMC_DLI_TRIM_TXDQS6 271 - description: EMC_DLI_TRIM_TXDQS7 272 - description: EMC_DLI_TRIM_TXDQS8 273 - description: EMC_DLI_TRIM_TXDQS9 274 - description: EMC_DLI_TRIM_TXDQS10 275 - description: EMC_DLI_TRIM_TXDQS11 276 - description: EMC_DLI_TRIM_TXDQS12 277 - description: EMC_DLI_TRIM_TXDQS13 278 - description: EMC_DLI_TRIM_TXDQS14 279 - description: EMC_DLI_TRIM_TXDQS15 280 - description: EMC_DLL_XFORM_DQ0 281 - description: EMC_DLL_XFORM_DQ1 282 - description: EMC_DLL_XFORM_DQ2 283 - description: EMC_DLL_XFORM_DQ3 284 - description: EMC_DLL_XFORM_DQ4 285 - description: EMC_DLL_XFORM_DQ5 286 - description: EMC_DLL_XFORM_DQ6 287 - description: EMC_DLL_XFORM_DQ7 288 - description: EMC_XM2CMDPADCTRL 289 - description: EMC_XM2CMDPADCTRL4 290 - description: EMC_XM2CMDPADCTRL5 291 - description: EMC_XM2DQPADCTRL2 292 - description: EMC_XM2DQPADCTRL3 293 - description: EMC_XM2CLKPADCTRL 294 - description: EMC_XM2CLKPADCTRL2 295 - description: EMC_XM2COMPPADCTRL 296 - description: EMC_XM2VTTGENPADCTRL 297 - description: EMC_XM2VTTGENPADCTRL2 298 - description: EMC_XM2VTTGENPADCTRL3 299 - description: EMC_XM2DQSPADCTRL3 300 - description: EMC_XM2DQSPADCTRL4 301 - description: EMC_XM2DQSPADCTRL5 302 - description: EMC_XM2DQSPADCTRL6 303 - description: EMC_DSR_VTTGEN_DRV 304 - description: EMC_TXDSRVTTGEN 305 - description: EMC_FBIO_SPARE 306 - description: EMC_ZCAL_WAIT_CNT 307 - description: EMC_MRS_WAIT_CNT2 308 - description: EMC_CTT 309 - description: EMC_CTT_DURATION 310 - description: EMC_CFG_PIPE 311 - description: EMC_DYN_SELF_REF_CONTROL 312 - description: EMC_QPOP 313 314 required: 315 - clock-frequency 316 - nvidia,emc-auto-cal-config 317 - nvidia,emc-auto-cal-config2 318 - nvidia,emc-auto-cal-config3 319 - nvidia,emc-auto-cal-interval 320 - nvidia,emc-bgbias-ctl0 321 - nvidia,emc-cfg 322 - nvidia,emc-cfg-2 323 - nvidia,emc-ctt-term-ctrl 324 - nvidia,emc-mode-1 325 - nvidia,emc-mode-2 326 - nvidia,emc-mode-4 327 - nvidia,emc-mode-reset 328 - nvidia,emc-mrs-wait-cnt 329 - nvidia,emc-sel-dpd-ctrl 330 - nvidia,emc-xm2dqspadctrl2 331 - nvidia,emc-zcal-cnt-long 332 - nvidia,emc-zcal-interval 333 - nvidia,emc-configuration 334 335 additionalProperties: false 336 337 required: 338 - compatible 339 - reg 340 - clocks 341 - clock-names 342 - nvidia,memory-controller 343 - "#interconnect-cells" 344 - operating-points-v2 345 346 additionalProperties: false 347 348 examples: 349 - | 350 #include <dt-bindings/clock/tegra124-car.h> 351 #include <dt-bindings/interrupt-controller/arm-gic.h> 352 353 mc: memory-controller@70019000 { 354 compatible = "nvidia,tegra124-mc"; 355 reg = <0x70019000 0x1000>; 356 clocks = <&tegra_car TEGRA124_CLK_MC>; 357 clock-names = "mc"; 358 359 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 360 361 #iommu-cells = <1>; 362 #reset-cells = <1>; 363 #interconnect-cells = <1>; 364 }; 365 366 external-memory-controller@7001b000 { 367 compatible = "nvidia,tegra124-emc"; 368 reg = <0x7001b000 0x1000>; 369 clocks = <&car TEGRA124_CLK_EMC>; 370 clock-names = "emc"; 371 372 nvidia,memory-controller = <&mc>; 373 operating-points-v2 = <&dvfs_opp_table>; 374 power-domains = <&domain>; 375 376 #interconnect-cells = <0>; 377 378 emc-timings-0 { 379 nvidia,ram-code = <3>; 380 381 timing-0 { 382 clock-frequency = <12750000>; 383 384 nvidia,emc-auto-cal-config = <0xa1430000>; 385 nvidia,emc-auto-cal-config2 = <0x00000000>; 386 nvidia,emc-auto-cal-config3 = <0x00000000>; 387 nvidia,emc-auto-cal-interval = <0x001fffff>; 388 nvidia,emc-bgbias-ctl0 = <0x00000008>; 389 nvidia,emc-cfg = <0x73240000>; 390 nvidia,emc-cfg-2 = <0x000008c5>; 391 nvidia,emc-ctt-term-ctrl = <0x00000802>; 392 nvidia,emc-mode-1 = <0x80100003>; 393 nvidia,emc-mode-2 = <0x80200008>; 394 nvidia,emc-mode-4 = <0x00000000>; 395 nvidia,emc-mode-reset = <0x80001221>; 396 nvidia,emc-mrs-wait-cnt = <0x000e000e>; 397 nvidia,emc-sel-dpd-ctrl = <0x00040128>; 398 nvidia,emc-xm2dqspadctrl2 = <0x0130b118>; 399 nvidia,emc-zcal-cnt-long = <0x00000042>; 400 nvidia,emc-zcal-interval = <0x00000000>; 401 402 nvidia,emc-configuration = < 403 0x00000000 /* EMC_RC */ 404 0x00000003 /* EMC_RFC */ 405 0x00000000 /* EMC_RFC_SLR */ 406 0x00000000 /* EMC_RAS */ 407 0x00000000 /* EMC_RP */ 408 0x00000004 /* EMC_R2W */ 409 0x0000000a /* EMC_W2R */ 410 0x00000003 /* EMC_R2P */ 411 0x0000000b /* EMC_W2P */ 412 0x00000000 /* EMC_RD_RCD */ 413 0x00000000 /* EMC_WR_RCD */ 414 0x00000003 /* EMC_RRD */ 415 0x00000003 /* EMC_REXT */ 416 0x00000000 /* EMC_WEXT */ 417 0x00000006 /* EMC_WDV */ 418 0x00000006 /* EMC_WDV_MASK */ 419 0x00000006 /* EMC_QUSE */ 420 0x00000002 /* EMC_QUSE_WIDTH */ 421 0x00000000 /* EMC_IBDLY */ 422 0x00000005 /* EMC_EINPUT */ 423 0x00000005 /* EMC_EINPUT_DURATION */ 424 0x00010000 /* EMC_PUTERM_EXTRA */ 425 0x00000003 /* EMC_PUTERM_WIDTH */ 426 0x00000000 /* EMC_PUTERM_ADJ */ 427 0x00000000 /* EMC_CDB_CNTL_1 */ 428 0x00000000 /* EMC_CDB_CNTL_2 */ 429 0x00000000 /* EMC_CDB_CNTL_3 */ 430 0x00000004 /* EMC_QRST */ 431 0x0000000c /* EMC_QSAFE */ 432 0x0000000d /* EMC_RDV */ 433 0x0000000f /* EMC_RDV_MASK */ 434 0x00000060 /* EMC_REFRESH */ 435 0x00000000 /* EMC_BURST_REFRESH_NUM */ 436 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */ 437 0x00000002 /* EMC_PDEX2WR */ 438 0x00000002 /* EMC_PDEX2RD */ 439 0x00000001 /* EMC_PCHG2PDEN */ 440 0x00000000 /* EMC_ACT2PDEN */ 441 0x00000007 /* EMC_AR2PDEN */ 442 0x0000000f /* EMC_RW2PDEN */ 443 0x00000005 /* EMC_TXSR */ 444 0x00000005 /* EMC_TXSRDLL */ 445 0x00000004 /* EMC_TCKE */ 446 0x00000005 /* EMC_TCKESR */ 447 0x00000004 /* EMC_TPD */ 448 0x00000000 /* EMC_TFAW */ 449 0x00000000 /* EMC_TRPAB */ 450 0x00000005 /* EMC_TCLKSTABLE */ 451 0x00000005 /* EMC_TCLKSTOP */ 452 0x00000064 /* EMC_TREFBW */ 453 0x00000000 /* EMC_FBIO_CFG6 */ 454 0x00000000 /* EMC_ODT_WRITE */ 455 0x00000000 /* EMC_ODT_READ */ 456 0x106aa298 /* EMC_FBIO_CFG5 */ 457 0x002c00a0 /* EMC_CFG_DIG_DLL */ 458 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ 459 0x00064000 /* EMC_DLL_XFORM_DQS0 */ 460 0x00064000 /* EMC_DLL_XFORM_DQS1 */ 461 0x00064000 /* EMC_DLL_XFORM_DQS2 */ 462 0x00064000 /* EMC_DLL_XFORM_DQS3 */ 463 0x00064000 /* EMC_DLL_XFORM_DQS4 */ 464 0x00064000 /* EMC_DLL_XFORM_DQS5 */ 465 0x00064000 /* EMC_DLL_XFORM_DQS6 */ 466 0x00064000 /* EMC_DLL_XFORM_DQS7 */ 467 0x00064000 /* EMC_DLL_XFORM_DQS8 */ 468 0x00064000 /* EMC_DLL_XFORM_DQS9 */ 469 0x00064000 /* EMC_DLL_XFORM_DQS10 */ 470 0x00064000 /* EMC_DLL_XFORM_DQS11 */ 471 0x00064000 /* EMC_DLL_XFORM_DQS12 */ 472 0x00064000 /* EMC_DLL_XFORM_DQS13 */ 473 0x00064000 /* EMC_DLL_XFORM_DQS14 */ 474 0x00064000 /* EMC_DLL_XFORM_DQS15 */ 475 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ 476 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ 477 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ 478 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ 479 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ 480 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ 481 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ 482 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ 483 0x00000000 /* EMC_DLL_XFORM_ADDR0 */ 484 0x00000000 /* EMC_DLL_XFORM_ADDR1 */ 485 0x00000000 /* EMC_DLL_XFORM_ADDR2 */ 486 0x00000000 /* EMC_DLL_XFORM_ADDR3 */ 487 0x00000000 /* EMC_DLL_XFORM_ADDR4 */ 488 0x00000000 /* EMC_DLL_XFORM_ADDR5 */ 489 0x00000000 /* EMC_DLL_XFORM_QUSE8 */ 490 0x00000000 /* EMC_DLL_XFORM_QUSE9 */ 491 0x00000000 /* EMC_DLL_XFORM_QUSE10 */ 492 0x00000000 /* EMC_DLL_XFORM_QUSE11 */ 493 0x00000000 /* EMC_DLL_XFORM_QUSE12 */ 494 0x00000000 /* EMC_DLL_XFORM_QUSE13 */ 495 0x00000000 /* EMC_DLL_XFORM_QUSE14 */ 496 0x00000000 /* EMC_DLL_XFORM_QUSE15 */ 497 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ 498 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ 499 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ 500 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ 501 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ 502 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ 503 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ 504 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ 505 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */ 506 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */ 507 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */ 508 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */ 509 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */ 510 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */ 511 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */ 512 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */ 513 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ 514 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ 515 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ 516 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ 517 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */ 518 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */ 519 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */ 520 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */ 521 0x10000280 /* EMC_XM2CMDPADCTRL */ 522 0x00000000 /* EMC_XM2CMDPADCTRL4 */ 523 0x00111111 /* EMC_XM2CMDPADCTRL5 */ 524 0x00000000 /* EMC_XM2DQPADCTRL2 */ 525 0x00000000 /* EMC_XM2DQPADCTRL3 */ 526 0x77ffc081 /* EMC_XM2CLKPADCTRL */ 527 0x00000e0e /* EMC_XM2CLKPADCTRL2 */ 528 0x81f1f108 /* EMC_XM2COMPPADCTRL */ 529 0x07070004 /* EMC_XM2VTTGENPADCTRL */ 530 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */ 531 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */ 532 0x51451400 /* EMC_XM2DQSPADCTRL3 */ 533 0x00514514 /* EMC_XM2DQSPADCTRL4 */ 534 0x00514514 /* EMC_XM2DQSPADCTRL5 */ 535 0x51451400 /* EMC_XM2DQSPADCTRL6 */ 536 0x0000003f /* EMC_DSR_VTTGEN_DRV */ 537 0x00000007 /* EMC_TXDSRVTTGEN */ 538 0x00000000 /* EMC_FBIO_SPARE */ 539 0x00000042 /* EMC_ZCAL_WAIT_CNT */ 540 0x000e000e /* EMC_MRS_WAIT_CNT2 */ 541 0x00000000 /* EMC_CTT */ 542 0x00000003 /* EMC_CTT_DURATION */ 543 0x0000f2f3 /* EMC_CFG_PIPE */ 544 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */ 545 0x0000000a /* EMC_QPOP */ 546 >; 547 }; 548 }; 549 };
Cache object: 3655aeae03ff4d453f33b1df7805a795
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