nvidia,tegra20-emc.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: NVIDIA Tegra20 SoC External Memory Controller
    8 
    9 maintainers:
   10   - Dmitry Osipenko <digetx@gmail.com>
   11   - Jon Hunter <jonathanh@nvidia.com>
   12   - Thierry Reding <thierry.reding@gmail.com>
   13 
   14 description: |
   15   The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
   16   service the request stream sent from Memory Controller. The EMC also has
   17   various performance-affecting settings beyond the obvious SDRAM configuration
   18   parameters and initialization settings. Tegra20 EMC supports multiple JEDEC
   19   standard protocols: DDR1, LPDDR2 and DDR2.
   20 
   21 properties:
   22   compatible:
   23     const: nvidia,tegra20-emc
   24 
   25   reg:
   26     maxItems: 1
   27 
   28   clocks:
   29     maxItems: 1
   30 
   31   interrupts:
   32     maxItems: 1
   33 
   34   "#address-cells":
   35     const: 1
   36 
   37   "#size-cells":
   38     const: 0
   39 
   40   "#interconnect-cells":
   41     const: 0
   42 
   43   nvidia,memory-controller:
   44     $ref: /schemas/types.yaml#/definitions/phandle
   45     description:
   46       Phandle of the Memory Controller node.
   47 
   48   power-domains:
   49     maxItems: 1
   50     description:
   51       Phandle of the SoC "core" power domain.
   52 
   53   operating-points-v2:
   54     description:
   55       Should contain freqs and voltages and opp-supported-hw property, which
   56       is a bitfield indicating SoC process ID mask.
   57 
   58   nvidia,use-ram-code:
   59     type: boolean
   60     description:
   61       If present, the emc-tables@ sub-nodes will be addressed.
   62 
   63 $defs:
   64   emc-table:
   65     type: object
   66     properties:
   67       compatible:
   68         const: nvidia,tegra20-emc-table
   69 
   70       clock-frequency:
   71         description:
   72           Memory clock rate in kHz.
   73         minimum: 1000
   74         maximum: 900000
   75 
   76       reg:
   77         maxItems: 1
   78         description:
   79           Either an opaque enumerator to tell different tables apart, or
   80           the valid frequency for which the table should be used (in kHz).
   81 
   82       nvidia,emc-registers:
   83         description:
   84           EMC timing characterization data. These are the registers
   85           (see section "15.4.1 EMC Registers" in the TRM) whose values
   86           need to be specified, according to the board documentation.
   87         $ref: /schemas/types.yaml#/definitions/uint32-array
   88         items:
   89           - description: EMC_RC
   90           - description: EMC_RFC
   91           - description: EMC_RAS
   92           - description: EMC_RP
   93           - description: EMC_R2W
   94           - description: EMC_W2R
   95           - description: EMC_R2P
   96           - description: EMC_W2P
   97           - description: EMC_RD_RCD
   98           - description: EMC_WR_RCD
   99           - description: EMC_RRD
  100           - description: EMC_REXT
  101           - description: EMC_WDV
  102           - description: EMC_QUSE
  103           - description: EMC_QRST
  104           - description: EMC_QSAFE
  105           - description: EMC_RDV
  106           - description: EMC_REFRESH
  107           - description: EMC_BURST_REFRESH_NUM
  108           - description: EMC_PDEX2WR
  109           - description: EMC_PDEX2RD
  110           - description: EMC_PCHG2PDEN
  111           - description: EMC_ACT2PDEN
  112           - description: EMC_AR2PDEN
  113           - description: EMC_RW2PDEN
  114           - description: EMC_TXSR
  115           - description: EMC_TCKE
  116           - description: EMC_TFAW
  117           - description: EMC_TRPAB
  118           - description: EMC_TCLKSTABLE
  119           - description: EMC_TCLKSTOP
  120           - description: EMC_TREFBW
  121           - description: EMC_QUSE_EXTRA
  122           - description: EMC_FBIO_CFG6
  123           - description: EMC_ODT_WRITE
  124           - description: EMC_ODT_READ
  125           - description: EMC_FBIO_CFG5
  126           - description: EMC_CFG_DIG_DLL
  127           - description: EMC_DLL_XFORM_DQS
  128           - description: EMC_DLL_XFORM_QUSE
  129           - description: EMC_ZCAL_REF_CNT
  130           - description: EMC_ZCAL_WAIT_CNT
  131           - description: EMC_AUTO_CAL_INTERVAL
  132           - description: EMC_CFG_CLKTRIM_0
  133           - description: EMC_CFG_CLKTRIM_1
  134           - description: EMC_CFG_CLKTRIM_2
  135 
  136     required:
  137       - clock-frequency
  138       - compatible
  139       - reg
  140       - nvidia,emc-registers
  141 
  142     additionalProperties: false
  143 
  144 patternProperties:
  145   "^emc-table@[0-9]+$":
  146     $ref: "#/$defs/emc-table"
  147 
  148   "^emc-tables@[a-z0-9-]+$":
  149     type: object
  150     properties:
  151       reg:
  152         maxItems: 1
  153         description:
  154           An opaque enumerator to tell different tables apart.
  155 
  156       nvidia,ram-code:
  157         $ref: /schemas/types.yaml#/definitions/uint32
  158         description:
  159           Value of RAM_CODE this timing set is used for.
  160 
  161       "#address-cells":
  162         const: 1
  163 
  164       "#size-cells":
  165         const: 0
  166 
  167       lpddr2:
  168         $ref: "ddr/jedec,lpddr2.yaml#"
  169         type: object
  170 
  171     patternProperties:
  172       "^emc-table@[0-9]+$":
  173         $ref: "#/$defs/emc-table"
  174 
  175     oneOf:
  176       - required:
  177           - nvidia,ram-code
  178 
  179       - required:
  180           - lpddr2
  181 
  182     additionalProperties: false
  183 
  184 required:
  185   - compatible
  186   - reg
  187   - interrupts
  188   - clocks
  189   - nvidia,memory-controller
  190   - "#interconnect-cells"
  191   - operating-points-v2
  192 
  193 additionalProperties: false
  194 
  195 examples:
  196   - |
  197     external-memory-controller@7000f400 {
  198         compatible = "nvidia,tegra20-emc";
  199         reg = <0x7000f400 0x400>;
  200         interrupts = <0 78 4>;
  201         clocks = <&clock_controller 57>;
  202 
  203         nvidia,memory-controller = <&mc>;
  204         operating-points-v2 = <&dvfs_opp_table>;
  205         power-domains = <&domain>;
  206 
  207         #interconnect-cells = <0>;
  208         #address-cells = <1>;
  209         #size-cells = <0>;
  210 
  211         nvidia,use-ram-code;
  212 
  213         emc-tables@0 {
  214             nvidia,ram-code = <0>;
  215             reg = <0>;
  216 
  217             #address-cells = <1>;
  218             #size-cells = <0>;
  219 
  220             emc-table@333000 {
  221                 reg = <333000>;
  222                 compatible = "nvidia,tegra20-emc-table";
  223                 clock-frequency = <333000>;
  224                 nvidia,emc-registers = <0x00000018 0x00000033
  225                         0x00000012 0x00000004 0x00000004 0x00000005
  226                         0x00000003 0x0000000c 0x00000006 0x00000006
  227                         0x00000003 0x00000001 0x00000004 0x00000005
  228                         0x00000004 0x00000009 0x0000000d 0x00000bff
  229                         0x00000000 0x00000003 0x00000003 0x00000006
  230                         0x00000006 0x00000001 0x00000011 0x000000c8
  231                         0x00000003 0x0000000e 0x00000007 0x00000008
  232                         0x00000002 0x00000000 0x00000000 0x00000002
  233                         0x00000000 0x00000000 0x00000083 0xf0440303
  234                         0x007fe010 0x00001414 0x00000000 0x00000000
  235                         0x00000000 0x00000000 0x00000000 0x00000000>;
  236             };
  237         };
  238 
  239         emc-tables@1 {
  240             reg = <1>;
  241 
  242             lpddr2 {
  243                 compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4";
  244                 revision-id1 = <1>;
  245                 density = <2048>;
  246                 io-width = <16>;
  247             };
  248         };
  249     };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/memory-controllers/nvidia,tegra20-emc.yaml

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sys/contrib/device-tree/Bindings/memory-controllers/nvidia,tegra20-emc.yaml