FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/memory-controllers/qca,ath79-ddr-controller.yaml

     # SPDX-License-Identifier: GPL-2.0
     %YAML 1.2
     ---
     $id: http://devicetree.org/schemas/memory-controllers/qca,ath79-ddr-controller.yaml#
     $schema: http://devicetree.org/meta-schemas/core.yaml#
     
     title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller
     
     maintainers:
      - Krzysztof Kozlowski <krzk@kernel.org>
    
    description: |
      The DDR controller of the AR7xxx and AR9xxx families provides an interface to
      flush the FIFO between various devices and the DDR. This is mainly used by
      the IRQ controller to flush the FIFO before running the interrupt handler of
      such devices.
    
    properties:
      compatible:
        oneOf:
          - items:
              - const: qca,ar9132-ddr-controller
              - const: qca,ar7240-ddr-controller
          - items:
              - enum:
                  - qca,ar7100-ddr-controller
                  - qca,ar7240-ddr-controller
    
      "#qca,ddr-wb-channel-cells":
        description: |
          Specifies the number of cells needed to encode the write buffer channel
          index.
        $ref: /schemas/types.yaml#/definitions/uint32
        const: 1
    
      reg:
        maxItems: 1
    
    required:
      - compatible
      - "#qca,ddr-wb-channel-cells"
      - reg
    
    additionalProperties: false
    
    examples:
      - |
        ddr_ctrl: memory-controller@18000000 {
            compatible = "qca,ar9132-ddr-controller",
                         "qca,ar7240-ddr-controller";
            reg = <0x18000000 0x100>;
    
            #qca,ddr-wb-channel-cells = <1>;
        };
    
        interrupt-controller {
            // ...
            qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
            qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
                                  <&ddr_ctrl 0>, <&ddr_ctrl 1>;
        };

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