renesas,dbsc.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: "http://devicetree.org/schemas/memory-controllers/renesas,dbsc.yaml#"
    5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
    6 
    7 title: Renesas DDR Bus Controllers
    8 
    9 maintainers:
   10   - Geert Uytterhoeven <geert+renesas@glider.be>
   11 
   12 description: |
   13   Renesas SoCs contain one or more memory controllers.  These memory
   14   controllers differ from one SoC variant to another, and are called by
   15   different names, e.g. "DDR Bus Controller (DBSC)", "DDR3 Bus State Controller
   16   (DBSC3)", or "SDRAM Bus State Controller (SBSC)").
   17 
   18 properties:
   19   compatible:
   20     enum:
   21       - renesas,dbsc-r8a73a4  # R-Mobile APE6
   22       - renesas,dbsc3-r8a7740 # R-Mobile A1
   23       - renesas,sbsc-sh73a0   # SH-Mobile AG5
   24 
   25   reg:
   26     maxItems: 1
   27 
   28   interrupts:
   29     maxItems: 2
   30 
   31   interrupt-names:
   32     items:
   33       - const: sec  # secure interrupt
   34       - const: temp # normal (temperature) interrupt
   35 
   36   power-domains:
   37     maxItems: 1
   38 
   39 required:
   40   - compatible
   41   - reg
   42   - power-domains
   43 
   44 additionalProperties: false
   45 
   46 examples:
   47   - |
   48     #include <dt-bindings/interrupt-controller/arm-gic.h>
   49     sbsc1: memory-controller@fe400000 {
   50             compatible = "renesas,sbsc-sh73a0";
   51             reg = <0xfe400000 0x400>;
   52             interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
   53                          <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
   54             interrupt-names = "sec", "temp";
   55             power-domains = <&pd_a4bc0>;
   56     };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/memory-controllers/renesas,dbsc.yaml

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sys/contrib/device-tree/Bindings/memory-controllers/renesas,dbsc.yaml