samsung,exynos5422-dmc.yaml

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    1 # SPDX-License-Identifier: GPL-2.0
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: |
    8   Samsung Exynos5422 SoC frequency and voltage scaling for Dynamic Memory
    9   Controller device
   10 
   11 maintainers:
   12   - Krzysztof Kozlowski <krzk@kernel.org>
   13   - Lukasz Luba <lukasz.luba@arm.com>
   14 
   15 description: |
   16   The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the
   17   DRAM memory chips are connected. The driver is to monitor the controller in
   18   runtime and switch frequency and voltage. To monitor the usage of the
   19   controller in runtime, the driver uses the PPMU (Platform Performance
   20   Monitoring Unit), which is able to measure the current load of the memory.
   21   When 'userspace' governor is used for the driver, an application is able to
   22   switch the DMC and memory frequency.
   23 
   24 properties:
   25   compatible:
   26     items:
   27       - const: samsung,exynos5422-dmc
   28 
   29   clock-names:
   30     items:
   31       - const: fout_spll
   32       - const: mout_sclk_spll
   33       - const: ff_dout_spll2
   34       - const: fout_bpll
   35       - const: mout_bpll
   36       - const: sclk_bpll
   37       - const: mout_mx_mspll_ccore
   38       - const: mout_mclk_cdrex
   39 
   40   clocks:
   41     minItems: 8
   42     maxItems: 8
   43 
   44   devfreq-events:
   45     $ref: '/schemas/types.yaml#/definitions/phandle-array'
   46     minItems: 1
   47     maxItems: 16
   48     items:
   49       maxItems: 1
   50     description: phandles of the PPMU events used by the controller.
   51 
   52   device-handle:
   53     $ref: '/schemas/types.yaml#/definitions/phandle'
   54     description: |
   55       phandle of the connected DRAM memory device. For more information please
   56       refer to jedec,lpddr3.yaml.
   57 
   58   operating-points-v2: true
   59 
   60   interrupts:
   61     items:
   62       - description: DMC internal performance event counters in DREX0
   63       - description: DMC internal performance event counters in DREX1
   64 
   65   interrupt-names:
   66     items:
   67       - const: drex_0
   68       - const: drex_1
   69 
   70   reg:
   71     items:
   72       - description: registers of DREX0
   73       - description: registers of DREX1
   74 
   75   samsung,syscon-clk:
   76     $ref: '/schemas/types.yaml#/definitions/phandle'
   77     description: |
   78       Phandle of the clock register set used by the controller, these registers
   79       are used for enabling a 'pause' feature and are not exposed by clock
   80       framework but they must be used in a safe way.  The register offsets are
   81       in the driver code and specyfic for this SoC type.
   82 
   83   vdd-supply: true
   84 
   85 required:
   86   - compatible
   87   - clock-names
   88   - clocks
   89   - devfreq-events
   90   - device-handle
   91   - reg
   92   - samsung,syscon-clk
   93 
   94 additionalProperties: false
   95 
   96 examples:
   97   - |
   98     #include <dt-bindings/clock/exynos5420.h>
   99     ppmu_dmc0_0: ppmu@10d00000 {
  100         compatible = "samsung,exynos-ppmu";
  101         reg = <0x10d00000 0x2000>;
  102         clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
  103         clock-names = "ppmu";
  104         events {
  105             ppmu_event_dmc0_0: ppmu-event3-dmc0-0 {
  106                 event-name = "ppmu-event3-dmc0_0";
  107             };
  108         };
  109     };
  110 
  111     memory-controller@10c20000 {
  112         compatible = "samsung,exynos5422-dmc";
  113         reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
  114         clocks = <&clock CLK_FOUT_SPLL>,
  115                  <&clock CLK_MOUT_SCLK_SPLL>,
  116                  <&clock CLK_FF_DOUT_SPLL2>,
  117                  <&clock CLK_FOUT_BPLL>,
  118                  <&clock CLK_MOUT_BPLL>,
  119                  <&clock CLK_SCLK_BPLL>,
  120                  <&clock CLK_MOUT_MX_MSPLL_CCORE>,
  121                  <&clock CLK_MOUT_MCLK_CDREX>;
  122         clock-names = "fout_spll",
  123                       "mout_sclk_spll",
  124                       "ff_dout_spll2",
  125                       "fout_bpll",
  126                       "mout_bpll",
  127                       "sclk_bpll",
  128                       "mout_mx_mspll_ccore",
  129                       "mout_mclk_cdrex";
  130         operating-points-v2 = <&dmc_opp_table>;
  131         devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
  132                          <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
  133         device-handle = <&samsung_K3QF2F20DB>;
  134         vdd-supply = <&buck1_reg>;
  135         samsung,syscon-clk = <&clock>;
  136         interrupt-parent = <&combiner>;
  137         interrupts = <16 0>, <16 1>;
  138         interrupt-names = "drex_0", "drex_1";
  139     };

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sys/contrib/device-tree/Bindings/memory-controllers/samsung,exynos5422-dmc.yaml