The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)

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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/mfd/samsung,exynos5433-lpass.txt

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    1 Samsung Exynos SoC Low Power Audio Subsystem (LPASS)
    2 
    3 Required properties:
    4 
    5  - compatible           : "samsung,exynos5433-lpass"
    6  - reg                  : should contain the LPASS top SFR region location
    7                           and size
    8  - clock-names          : should contain following required clocks: "sfr0_ctrl"
    9  - clocks               : should contain clock specifiers of all clocks, which
   10                           input names have been specified in clock-names
   11                           property, in same order.
   12  - #address-cells       : should be 1
   13  - #size-cells          : should be 1
   14  - ranges               : must be present
   15 
   16 Each IP block of the Low Power Audio Subsystem should be specified as
   17 an optional sub-node. For "samsung,exynos5433-lpass" compatible this includes:
   18 UART, SLIMBUS, PCM, I2S, DMAC, Timers 0...4, VIC, WDT 0...1 devices.
   19 
   20 Bindings of the sub-nodes are described in:
   21   ../serial/samsung_uart.yaml
   22   ../sound/samsung-i2s.txt
   23   ../dma/arm-pl330.txt
   24 
   25 
   26 Example:
   27 
   28 audio-subsystem {
   29         compatible = "samsung,exynos5433-lpass";
   30         reg = <0x11400000 0x100>, <0x11500000 0x08>;
   31         clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
   32         clock-names = "sfr0_ctrl";
   33         #address-cells = <1>;
   34         #size-cells = <1>;
   35         ranges;
   36 
   37         adma: adma@11420000 {
   38                 compatible = "arm,pl330", "arm,primecell";
   39                 reg = <0x11420000 0x1000>;
   40                 interrupts = <0 73 0>;
   41                 clocks = <&cmu_aud CLK_ACLK_DMAC>;
   42                 clock-names = "apb_pclk";
   43                 #dma-cells = <1>;
   44                 #dma-channels = <8>;
   45                 #dma-requests = <32>;
   46         };
   47 
   48         i2s0: i2s0@11440000 {
   49                 compatible = "samsung,exynos7-i2s";
   50                 reg = <0x11440000 0x100>;
   51                 dmas = <&adma 0 &adma 2>;
   52                 dma-names = "tx", "rx";
   53                 interrupts = <0 70 0>;
   54                 clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
   55                          <&cmu_aud CLK_SCLK_AUD_I2S>,
   56                          <&cmu_aud CLK_SCLK_I2S_BCLK>;
   57                 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
   58                 pinctrl-names = "default";
   59                 pinctrl-0 = <&i2s0_bus>;
   60         };
   61 
   62         serial_3: serial@11460000 {
   63                 compatible = "samsung,exynos5433-uart";
   64                 reg = <0x11460000 0x100>;
   65                 interrupts = <0 67 0>;
   66                 clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
   67                          <&cmu_aud CLK_SCLK_AUD_UART>;
   68                 clock-names = "uart", "clk_uart_baud0";
   69                 pinctrl-names = "default";
   70                 pinctrl-0 = <&uart_aud_bus>;
   71         };
   72  };

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