cib.txt

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    1 * Cavium Interrupt Bus widget
    2 
    3 Properties:
    4 - compatible: "cavium,octeon-7130-cib"
    5 
    6   Compatibility with cn70XX SoCs.
    7 
    8 - interrupt-controller:  This is an interrupt controller.
    9 
   10 - reg: Two elements consisting of the addresses of the RAW and EN
   11   registers of the CIB block
   12 
   13 - cavium,max-bits: The index (zero based) of the highest numbered bit
   14   in the CIB block.
   15 
   16 - interrupts: The CIU line to which the CIB block is connected.
   17 
   18 - #interrupt-cells: Must be <2>.  The first cell is the bit within the
   19    CIB.  The second cell specifies the triggering semantics of the
   20    line.
   21 
   22 Example:
   23 
   24         interrupt-controller@107000000e000 {
   25                 compatible = "cavium,octeon-7130-cib";
   26                 reg = <0x10700 0x0000e000 0x0 0x8>, /* RAW */
   27                       <0x10700 0x0000e100 0x0 0x8>; /* EN */
   28                 cavium,max-bits = <23>;
   29 
   30                 interrupt-controller;
   31                 interrupt-parent = <&ciu>;
   32                 interrupts = <1 24>;
   33                 /* Interrupts are specified by two parts:
   34                  * 1) Bit number in the CIB* registers
   35                  * 2) Triggering (1 - edge rising
   36                  *                2 - edge falling
   37                  *                4 - level active high
   38                  *                8 - level active low)
   39                  */
   40                 #interrupt-cells = <2>;
   41         };

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sys/contrib/device-tree/Bindings/mips/cavium/cib.txt