amlogic,meson-gx.txt

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    1 Amlogic SD / eMMC controller for S905/GXBB family SoCs
    2 
    3 The MMC 5.1 compliant host controller on Amlogic provides the
    4 interface for SD, eMMC and SDIO devices.
    5 
    6 This file documents the properties in addition to those available in
    7 the MMC core bindings, documented by mmc.txt.
    8 
    9 Required properties:
   10 - compatible : contains one of:
   11   - "amlogic,meson-gx-mmc"
   12   - "amlogic,meson-gxbb-mmc"
   13   - "amlogic,meson-gxl-mmc"
   14   - "amlogic,meson-gxm-mmc"
   15   - "amlogic,meson-axg-mmc"
   16 - clocks     : A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
   17 - clock-names: Should contain the following:
   18         "core" - Main peripheral bus clock
   19         "clkin0" - Parent clock of internal mux
   20         "clkin1" - Other parent clock of internal mux
   21   The driver has an internal mux clock which switches between clkin0 and clkin1 depending on the
   22   clock rate requested by the MMC core.
   23 - resets     : phandle of the internal reset line
   24 
   25 Optional properties:
   26 - amlogic,dram-access-quirk: set when controller's internal DMA engine cannot access the
   27   DRAM memory, like on the G12A dedicated SDIO controller.
   28 
   29 Example:
   30 
   31         sd_emmc_a: mmc@70000 {
   32                 compatible = "amlogic,meson-gxbb-mmc";
   33                 reg = <0x0 0x70000 0x0 0x2000>;
   34                 interrupts = < GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
   35                 clocks = <&clkc CLKID_SD_EMMC_A>, <&xtal>, <&clkc CLKID_FCLK_DIV2>;
   36                 clock-names = "core", "clkin0", "clkin1";
   37                 pinctrl-0 = <&emmc_pins>;
   38                 resets = <&reset RESET_SD_EMMC_A>;
   39         };

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