1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/mmc/arm,pl18x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: ARM PrimeCell MultiMedia Card Interface (MMCI) PL180 and PL181
8
9 maintainers:
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Ulf Hansson <ulf.hansson@linaro.org>
12
13 description:
14 The ARM PrimeCells MMCI PL180 and PL181 provides an interface for
15 reading and writing to MultiMedia and SD cards alike. Over the years
16 vendors have use the VHDL code from ARM to create derivative MMC/SD/SDIO
17 host controllers with very similar characteristics.
18
19 allOf:
20 - $ref: /schemas/arm/primecell.yaml#
21 - $ref: mmc-controller.yaml#
22
23 # We need a select here so we don't match all nodes with 'arm,primecell'
24 select:
25 properties:
26 compatible:
27 contains:
28 enum:
29 - arm,pl180
30 - arm,pl181
31 - arm,pl18x
32 required:
33 - compatible
34
35 properties:
36 compatible:
37 oneOf:
38 - description: The first version of the block, simply called
39 PL180 and found in the ARM Integrator IM/PD1 logic module.
40 items:
41 - const: arm,pl180
42 - const: arm,primecell
43 - description: The improved version of the block, found in the
44 ARM Versatile and later reference designs. Further revisions
45 exist but get detected at runtime by reading some magic numbers
46 in the PrimeCell ID registers.
47 items:
48 - const: arm,pl181
49 - const: arm,primecell
50 - description: Wildcard entry that will let the operating system
51 inspect the PrimeCell ID registers to determine which hardware
52 variant of PL180 or PL181 this is.
53 items:
54 - const: arm,pl18x
55 - const: arm,primecell
56 - description: Entry for STMicroelectronics variant of PL18x.
57 This dedicated compatible is used by bootloaders.
58 items:
59 - const: st,stm32-sdmmc2
60 - const: arm,pl18x
61 - const: arm,primecell
62
63 clocks:
64 description: One or two clocks, the "apb_pclk" and the "MCLK"
65 which is the core block clock. The names are not compulsory.
66 minItems: 1
67 maxItems: 2
68
69 dmas:
70 maxItems: 2
71
72 dma-names:
73 oneOf:
74 - items:
75 - const: tx
76 - const: rx
77 - items:
78 - const: rx
79 - const: tx
80
81 power-domains: true
82
83 resets:
84 maxItems: 1
85
86 reg:
87 description: the MMIO memory window must be exactly 4KB (0x1000) and the
88 layout should provide the PrimeCell ID registers so that the device can
89 be discovered. On ST Micro variants, a second register window may be
90 defined if a delay block is present and used for tuning.
91
92 interrupts:
93 description: The first interrupt is the command interrupt and corresponds
94 to the event at the end of a command. The second interrupt is the
95 PIO (polled I/O) interrupt and occurs when the FIFO needs to be
96 emptied as part of a bulk read from the card. Some variants have these
97 two interrupts wired into the same line (logic OR) and in that case
98 only one interrupt may be provided.
99 minItems: 1
100 maxItems: 2
101
102 st,sig-dir-dat0:
103 $ref: /schemas/types.yaml#/definitions/flag
104 description: ST Micro-specific property, bus signal direction pins used for
105 DAT[0].
106
107 st,sig-dir-dat2:
108 $ref: /schemas/types.yaml#/definitions/flag
109 description: ST Micro-specific property, bus signal direction pins used for
110 DAT[2].
111
112 st,sig-dir-dat31:
113 $ref: /schemas/types.yaml#/definitions/flag
114 description: ST Micro-specific property, bus signal direction pins used for
115 DAT[3] and DAT[1].
116
117 st,sig-dir-dat74:
118 $ref: /schemas/types.yaml#/definitions/flag
119 description: ST Micro-specific property, bus signal direction pins used for
120 DAT[7] and DAT[4].
121
122 st,sig-dir-cmd:
123 $ref: /schemas/types.yaml#/definitions/flag
124 description: ST Micro-specific property, CMD signal direction used for
125 pin CMD.
126
127 st,sig-pin-fbclk:
128 $ref: /schemas/types.yaml#/definitions/flag
129 description: ST Micro-specific property, feedback clock FBCLK signal pin
130 in use.
131
132 st,sig-dir:
133 $ref: /schemas/types.yaml#/definitions/flag
134 description: ST Micro-specific property, signal direction polarity used for
135 pins CMD, DAT[0], DAT[1], DAT[2] and DAT[3].
136
137 st,neg-edge:
138 $ref: /schemas/types.yaml#/definitions/flag
139 description: ST Micro-specific property, data and command phase relation,
140 generated on the sd clock falling edge.
141
142 st,use-ckin:
143 $ref: /schemas/types.yaml#/definitions/flag
144 description: ST Micro-specific property, use CKIN pin from an external
145 driver to sample the receive data (for example with a voltage switch
146 transceiver).
147
148 st,cmd-gpios:
149 maxItems: 1
150 description:
151 The GPIO matching the CMD pin.
152
153 st,ck-gpios:
154 maxItems: 1
155 description:
156 The GPIO matching the CK pin.
157
158 st,ckin-gpios:
159 maxItems: 1
160 description:
161 The GPIO matching the CKIN pin.
162
163 dependencies:
164 st,cmd-gpios: [ "st,use-ckin" ]
165 st,ck-gpios: [ "st,use-ckin" ]
166 st,ckin-gpios: [ "st,use-ckin" ]
167
168 unevaluatedProperties: false
169
170 required:
171 - compatible
172 - reg
173 - interrupts
174
175 examples:
176 - |
177 #include <dt-bindings/interrupt-controller/irq.h>
178 #include <dt-bindings/gpio/gpio.h>
179
180 mmc@5000 {
181 compatible = "arm,pl180", "arm,primecell";
182 reg = <0x5000 0x1000>;
183 interrupts-extended = <&vic 22 &sic 1>;
184 clocks = <&xtal24mhz>, <&pclk>;
185 clock-names = "mclk", "apb_pclk";
186 };
187
188 - |
189 #include <dt-bindings/interrupt-controller/irq.h>
190
191 mmc@80126000 {
192 compatible = "arm,pl18x", "arm,primecell";
193 reg = <0x80126000 0x1000>;
194 interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
195 dmas = <&dma 29 0 0x2>, <&dma 29 0 0x0>;
196 dma-names = "rx", "tx";
197 clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
198 clock-names = "sdi", "apb_pclk";
199 max-frequency = <100000000>;
200 bus-width = <4>;
201 cap-sd-highspeed;
202 cap-mmc-highspeed;
203 cd-gpios = <&gpio2 31 0x4>;
204 st,sig-dir-dat0;
205 st,sig-dir-dat2;
206 st,sig-dir-cmd;
207 st,sig-pin-fbclk;
208 vmmc-supply = <&ab8500_ldo_aux3_reg>;
209 vqmmc-supply = <&vmmci>;
210 };
211
212 - |
213 mmc@101f6000 {
214 compatible = "arm,pl18x", "arm,primecell";
215 reg = <0x101f6000 0x1000>;
216 clocks = <&sdiclk>, <&pclksdi>;
217 clock-names = "mclk", "apb_pclk";
218 interrupts = <22>;
219 max-frequency = <400000>;
220 bus-width = <4>;
221 cap-mmc-highspeed;
222 cap-sd-highspeed;
223 full-pwr-cycle;
224 st,sig-dir-dat0;
225 st,sig-dir-dat2;
226 st,sig-dir-dat31;
227 st,sig-dir-cmd;
228 st,sig-pin-fbclk;
229 vmmc-supply = <&vmmc_regulator>;
230 };
231
232 - |
233 mmc@52007000 {
234 compatible = "arm,pl18x", "arm,primecell";
235 arm,primecell-periphid = <0x10153180>;
236 reg = <0x52007000 0x1000>;
237 interrupts = <49>;
238 clocks = <&rcc 0>;
239 clock-names = "apb_pclk";
240 resets = <&rcc 1>;
241 cap-sd-highspeed;
242 cap-mmc-highspeed;
243 max-frequency = <120000000>;
244 };
Cache object: 77840110b5dd10a7088e37be1e14bebc
|