The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/mmc/exynos-dw-mshc.txt

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    1 * Samsung Exynos specific extensions to the Synopsys Designware Mobile
    2   Storage Host Controller
    3 
    4 The Synopsys designware mobile storage host controller is used to interface
    5 a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
    6 differences between the core Synopsys dw mshc controller properties described
    7 by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
    8 extensions to the Synopsys Designware Mobile Storage Host Controller.
    9 
   10 Required Properties:
   11 
   12 * compatible: should be
   13         - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
   14           specific extensions.
   15         - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
   16           specific extensions.
   17         - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
   18           specific extensions.
   19         - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
   20           specific extensions.
   21         - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
   22           specific extensions.
   23         - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
   24           specific extensions having an SMU.
   25         - "axis,artpec8-dw-mshc": for controllers with ARTPEC-8 specific
   26           extensions.
   27 
   28 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
   29   unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
   30   ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7.
   31 
   32 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
   33   in transmit mode and CIU clock phase shift value in receive mode for single
   34   data rate mode operation. Refer notes below for the order of the cells and the
   35   valid values.
   36 
   37 * samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
   38   in transmit mode and CIU clock phase shift value in receive mode for double
   39   data rate mode operation. Refer notes below for the order of the cells and the
   40   valid values.
   41 * samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
   42   shift value for hs400 mode operation.
   43 
   44   Notes for the sdr-timing and ddr-timing values:
   45 
   46     The order of the cells should be
   47       - First Cell: CIU clock phase shift value for tx mode.
   48       - Second Cell: CIU clock phase shift value for rx mode.
   49 
   50     Valid values for SDR and DDR CIU clock timing for Exynos5250:
   51       - valid value for tx phase shift and rx phase shift is 0 to 7.
   52       - when CIU clock divider value is set to 3, all possible 8 phase shift
   53         values can be used.
   54       - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
   55         phase shift clocks should be 0.
   56 
   57 * samsung,read-strobe-delay: RCLK (Data strobe) delay to control HS400 mode
   58   (Latency value for delay line in Read path)
   59 
   60 Required properties for a slot (Deprecated - Recommend to use one slot per host):
   61 
   62 * gpios: specifies a list of gpios used for command, clock and data bus. The
   63   first gpio is the command line and the second gpio is the clock line. The
   64   rest of the gpios (depending on the bus-width property) are the data lines in
   65   no particular order. The format of the gpio specifier depends on the gpio
   66   controller.
   67 (Deprecated - Refer to Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt)
   68 
   69 Example:
   70 
   71   The MSHC controller node can be split into two portions, SoC specific and
   72   board specific portions as listed below.
   73 
   74         dwmmc0@12200000 {
   75                 compatible = "samsung,exynos5250-dw-mshc";
   76                 reg = <0x12200000 0x1000>;
   77                 interrupts = <0 75 0>;
   78                 #address-cells = <1>;
   79                 #size-cells = <0>;
   80         };
   81 
   82         dwmmc0@12200000 {
   83                 cap-mmc-highspeed;
   84                 cap-sd-highspeed;
   85                 broken-cd;
   86                 fifo-depth = <0x80>;
   87                 card-detect-delay = <200>;
   88                 samsung,dw-mshc-ciu-div = <3>;
   89                 samsung,dw-mshc-sdr-timing = <2 3>;
   90                 samsung,dw-mshc-ddr-timing = <1 2>;
   91                 samsung,dw-mshc-hs400-timing = <0 2>;
   92                 samsung,read-strobe-delay = <90>;
   93                 bus-width = <8>;
   94         };

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