mtk-sd.yaml

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    1 # SPDX-License-Identifier: GPL-2.0
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: MTK MSDC Storage Host Controller Binding
    8 
    9 maintainers:
   10   - Chaotian Jing <chaotian.jing@mediatek.com>
   11   - Wenbin Mei <wenbin.mei@mediatek.com>
   12 
   13 allOf:
   14   - $ref: mmc-controller.yaml#
   15 
   16 properties:
   17   compatible:
   18     oneOf:
   19       - enum:
   20           - mediatek,mt2701-mmc
   21           - mediatek,mt2712-mmc
   22           - mediatek,mt6779-mmc
   23           - mediatek,mt7620-mmc
   24           - mediatek,mt7622-mmc
   25           - mediatek,mt8135-mmc
   26           - mediatek,mt8173-mmc
   27           - mediatek,mt8183-mmc
   28           - mediatek,mt8516-mmc
   29       - items:
   30           - const: mediatek,mt7623-mmc
   31           - const: mediatek,mt2701-mmc
   32       - items:
   33           - enum:
   34               - mediatek,mt8186-mmc
   35               - mediatek,mt8188-mmc
   36               - mediatek,mt8192-mmc
   37               - mediatek,mt8195-mmc
   38           - const: mediatek,mt8183-mmc
   39 
   40   reg:
   41     minItems: 1
   42     items:
   43       - description: base register (required).
   44       - description: top base register (required for MT8183).
   45 
   46   clocks:
   47     description:
   48       Should contain phandle for the clock feeding the MMC controller.
   49     minItems: 2
   50     items:
   51       - description: source clock (required).
   52       - description: HCLK which used for host (required).
   53       - description: independent source clock gate (required for MT2712).
   54       - description: bus clock used for internal register access (required for MT2712 MSDC0/3).
   55       - description: msdc subsys clock gate (required for MT8192).
   56       - description: peripheral bus clock gate (required for MT8192).
   57       - description: AXI bus clock gate (required for MT8192).
   58       - description: AHB bus clock gate (required for MT8192).
   59 
   60   clock-names:
   61     minItems: 2
   62     items:
   63       - const: source
   64       - const: hclk
   65       - const: source_cg
   66       - const: bus_clk
   67       - const: sys_cg
   68       - const: pclk_cg
   69       - const: axi_cg
   70       - const: ahb_cg
   71 
   72   interrupts:
   73     description:
   74       Should at least contain MSDC GIC interrupt. To support SDIO in-band wakeup, an extended
   75       interrupt is required and be configured as wakeup source irq.
   76     minItems: 1
   77     maxItems: 2
   78 
   79   interrupt-names:
   80     items:
   81       - const: msdc
   82       - const: sdio_wakeup
   83 
   84   pinctrl-names:
   85     description:
   86       Should at least contain default and state_uhs. To support SDIO in-band wakeup, dat1 pin
   87       will be switched between GPIO mode and SDIO DAT1 mode, state_eint is mandatory in this
   88       scenario.
   89     minItems: 2
   90     items:
   91       - const: default
   92       - const: state_uhs
   93       - const: state_eint
   94 
   95   pinctrl-0:
   96     description:
   97       should contain default/high speed pin ctrl.
   98     maxItems: 1
   99 
  100   pinctrl-1:
  101     description:
  102       should contain uhs mode pin ctrl.
  103     maxItems: 1
  104 
  105   pinctrl-2:
  106     description:
  107       should switch dat1 pin to GPIO mode.
  108     maxItems: 1
  109 
  110   assigned-clocks:
  111     description:
  112       PLL of the source clock.
  113     maxItems: 1
  114 
  115   assigned-clock-parents:
  116     description:
  117       parent of source clock, used for HS400 mode to get 400Mhz source clock.
  118     maxItems: 1
  119 
  120   hs400-ds-delay:
  121     $ref: /schemas/types.yaml#/definitions/uint32
  122     description:
  123       HS400 DS delay setting.
  124     minimum: 0
  125     maximum: 0xffffffff
  126 
  127   mediatek,hs200-cmd-int-delay:
  128     $ref: /schemas/types.yaml#/definitions/uint32
  129     description:
  130       HS200 command internal delay setting.
  131       This field has total 32 stages.
  132       The value is an integer from 0 to 31.
  133     minimum: 0
  134     maximum: 31
  135 
  136   mediatek,hs400-cmd-int-delay:
  137     $ref: /schemas/types.yaml#/definitions/uint32
  138     description:
  139       HS400 command internal delay setting.
  140       This field has total 32 stages.
  141       The value is an integer from 0 to 31.
  142     minimum: 0
  143     maximum: 31
  144 
  145   mediatek,hs400-cmd-resp-sel-rising:
  146     $ref: /schemas/types.yaml#/definitions/flag
  147     description:
  148       HS400 command response sample selection.
  149       If present, HS400 command responses are sampled on rising edges.
  150       If not present, HS400 command responses are sampled on falling edges.
  151 
  152   mediatek,hs400-ds-dly3:
  153     $ref: /schemas/types.yaml#/definitions/uint32
  154     description:
  155       Gear of the third delay line for DS for input data latch in data
  156       pad macro, there are 32 stages from 0 to 31.
  157       For different corner IC, the time is different about one step, it is
  158       about 100ps.
  159       The value is confirmed by doing scan and calibration to find a best
  160       value with corner IC and it is valid only for HS400 mode.
  161     minimum: 0
  162     maximum: 31
  163 
  164   mediatek,latch-ck:
  165     $ref: /schemas/types.yaml#/definitions/uint32
  166     description:
  167       Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
  168       data crc error caused by stop clock(fifo full) Valid range = [0:0x7].
  169       if not present, default value is 0.
  170       applied to compatible "mediatek,mt2701-mmc".
  171     minimum: 0
  172     maximum: 7
  173 
  174   resets:
  175     maxItems: 1
  176 
  177   reset-names:
  178     const: hrst
  179 
  180 required:
  181   - compatible
  182   - reg
  183   - interrupts
  184   - clocks
  185   - clock-names
  186   - pinctrl-names
  187   - pinctrl-0
  188   - pinctrl-1
  189   - vmmc-supply
  190   - vqmmc-supply
  191 
  192 if:
  193   properties:
  194     compatible:
  195       contains:
  196         const: mediatek,mt8183-mmc
  197 then:
  198   properties:
  199     reg:
  200       minItems: 2
  201 
  202 unevaluatedProperties: false
  203 
  204 examples:
  205   - |
  206     #include <dt-bindings/interrupt-controller/irq.h>
  207     #include <dt-bindings/interrupt-controller/arm-gic.h>
  208     #include <dt-bindings/clock/mt8173-clk.h>
  209     mmc0: mmc@11230000 {
  210         compatible = "mediatek,mt8173-mmc";
  211         reg = <0x11230000 0x1000>;
  212         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
  213         vmmc-supply = <&mt6397_vemc_3v3_reg>;
  214         vqmmc-supply = <&mt6397_vio18_reg>;
  215         clocks = <&pericfg CLK_PERI_MSDC30_0>,
  216                  <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
  217         clock-names = "source", "hclk";
  218         pinctrl-names = "default", "state_uhs";
  219         pinctrl-0 = <&mmc0_pins_default>;
  220         pinctrl-1 = <&mmc0_pins_uhs>;
  221         assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
  222         assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
  223         hs400-ds-delay = <0x14015>;
  224         mediatek,hs200-cmd-int-delay = <26>;
  225         mediatek,hs400-cmd-int-delay = <14>;
  226         mediatek,hs400-cmd-resp-sel-rising;
  227     };
  228 
  229     mmc3: mmc@11260000 {
  230         compatible = "mediatek,mt8173-mmc";
  231         reg = <0x11260000 0x1000>;
  232         clock-names = "source", "hclk";
  233         clocks = <&pericfg CLK_PERI_MSDC30_3>,
  234                  <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
  235         interrupt-names = "msdc", "sdio_wakeup";
  236         interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_LOW 0>,
  237                      <&pio 23 IRQ_TYPE_LEVEL_LOW>;
  238         pinctrl-names = "default", "state_uhs", "state_eint";
  239         pinctrl-0 = <&mmc2_pins_default>;
  240         pinctrl-1 = <&mmc2_pins_uhs>;
  241         pinctrl-2 = <&mmc2_pins_eint>;
  242         bus-width = <4>;
  243         max-frequency = <200000000>;
  244         cap-sd-highspeed;
  245         sd-uhs-sdr104;
  246         keep-power-in-suspend;
  247         wakeup-source;
  248         cap-sdio-irq;
  249         no-mmc;
  250         no-sd;
  251         non-removable;
  252         vmmc-supply = <&sdio_fixed_3v3>;
  253         vqmmc-supply = <&mt6397_vgp3_reg>;
  254         mmc-pwrseq = <&wifi_pwrseq>;
  255     };
  256 
  257 ...

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sys/contrib/device-tree/Bindings/mmc/mtk-sd.yaml