The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/mmc/renesas,sdhi.txt

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    1 * Renesas SDHI SD/MMC controller
    2 
    3 Required properties:
    4 - compatible: should contain one or more of the following:
    5                 "renesas,sdhi-sh73a0" - SDHI IP on SH73A0 SoC
    6                 "renesas,sdhi-r7s72100" - SDHI IP on R7S72100 SoC
    7                 "renesas,sdhi-r7s9210" - SDHI IP on R7S9210 SoC
    8                 "renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC
    9                 "renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC
   10                 "renesas,sdhi-r8a7742" - SDHI IP on R8A7742 SoC
   11                 "renesas,sdhi-r8a7743" - SDHI IP on R8A7743 SoC
   12                 "renesas,sdhi-r8a7744" - SDHI IP on R8A7744 SoC
   13                 "renesas,sdhi-r8a7745" - SDHI IP on R8A7745 SoC
   14                 "renesas,sdhi-r8a774a1" - SDHI IP on R8A774A1 SoC
   15                 "renesas,sdhi-r8a774b1" - SDHI IP on R8A774B1 SoC
   16                 "renesas,sdhi-r8a774c0" - SDHI IP on R8A774C0 SoC
   17                 "renesas,sdhi-r8a77470" - SDHI IP on R8A77470 SoC
   18                 "renesas,sdhi-mmc-r8a77470" - SDHI/MMC IP on R8A77470 SoC
   19                 "renesas,sdhi-r8a7778" - SDHI IP on R8A7778 SoC
   20                 "renesas,sdhi-r8a7779" - SDHI IP on R8A7779 SoC
   21                 "renesas,sdhi-r8a7790" - SDHI IP on R8A7790 SoC
   22                 "renesas,sdhi-r8a7791" - SDHI IP on R8A7791 SoC
   23                 "renesas,sdhi-r8a7792" - SDHI IP on R8A7792 SoC
   24                 "renesas,sdhi-r8a7793" - SDHI IP on R8A7793 SoC
   25                 "renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC
   26                 "renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC
   27                 "renesas,sdhi-r8a7796" - SDHI IP on R8A77960 SoC
   28                 "renesas,sdhi-r8a77961" - SDHI IP on R8A77961 SoC
   29                 "renesas,sdhi-r8a77965" - SDHI IP on R8A77965 SoC
   30                 "renesas,sdhi-r8a77970" - SDHI IP on R8A77970 SoC
   31                 "renesas,sdhi-r8a77980" - SDHI IP on R8A77980 SoC
   32                 "renesas,sdhi-r8a77990" - SDHI IP on R8A77990 SoC
   33                 "renesas,sdhi-r8a77995" - SDHI IP on R8A77995 SoC
   34                 "renesas,sdhi-shmobile" - a generic sh-mobile SDHI controller
   35                 "renesas,rcar-gen1-sdhi" - a generic R-Car Gen1 SDHI controller
   36                 "renesas,rcar-gen2-sdhi" - a generic R-Car Gen2 and RZ/G1 SDHI
   37                                            (not SDHI/MMC) controller
   38                 "renesas,rcar-gen3-sdhi" - a generic R-Car Gen3 or RZ/G2
   39                                            SDHI controller
   40 
   41 
   42                 When compatible with the generic version, nodes must list
   43                 the SoC-specific version corresponding to the platform
   44                 first followed by the generic version.
   45 
   46 - clocks: Most controllers only have 1 clock source per channel. However, on
   47           some variations of this controller, the internal card detection
   48           logic that exists in this controller is sectioned off to be run by a
   49           separate second clock source to allow the main core clock to be turned
   50           off to save power.
   51           If 2 clocks are specified by the hardware, you must name them as
   52           "core" and "cd". If the controller only has 1 clock, naming is not
   53           required.
   54           Devices which have more than 1 clock are listed below:
   55           2: R7S72100, R7S9210
   56 
   57 Optional properties:
   58 - pinctrl-names: should be "default", "state_uhs"
   59 - pinctrl-0: should contain default/high speed pin ctrl
   60 - pinctrl-1: should contain uhs mode pin ctrl
   61 
   62 Example: R8A7790 (R-Car H2) SDHI controller nodes
   63 
   64         sdhi0: sd@ee100000 {
   65                 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
   66                 reg = <0 0xee100000 0 0x328>;
   67                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
   68                 clocks = <&cpg CPG_MOD 314>;
   69                 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
   70                        <&dmac1 0xcd>, <&dmac1 0xce>;
   71                 dma-names = "tx", "rx", "tx", "rx";
   72                 max-frequency = <195000000>;
   73                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
   74                 resets = <&cpg 314>;
   75         };
   76 
   77         sdhi1: sd@ee120000 {
   78                 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
   79                 reg = <0 0xee120000 0 0x328>;
   80                 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
   81                 clocks = <&cpg CPG_MOD 313>;
   82                 dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
   83                        <&dmac1 0xc9>, <&dmac1 0xca>;
   84                 dma-names = "tx", "rx", "tx", "rx";
   85                 max-frequency = <195000000>;
   86                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
   87                 resets = <&cpg 313>;
   88         };
   89 
   90         sdhi2: sd@ee140000 {
   91                 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
   92                 reg = <0 0xee140000 0 0x100>;
   93                 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
   94                 clocks = <&cpg CPG_MOD 312>;
   95                 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
   96                        <&dmac1 0xc1>, <&dmac1 0xc2>;
   97                 dma-names = "tx", "rx", "tx", "rx";
   98                 max-frequency = <97500000>;
   99                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
  100                 resets = <&cpg 312>;
  101         };
  102 
  103         sdhi3: sd@ee160000 {
  104                 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
  105                 reg = <0 0xee160000 0 0x100>;
  106                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
  107                 clocks = <&cpg CPG_MOD 311>;
  108                 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
  109                        <&dmac1 0xd3>, <&dmac1 0xd4>;
  110                 dma-names = "tx", "rx", "tx", "rx";
  111                 max-frequency = <97500000>;
  112                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
  113                 resets = <&cpg 311>;
  114         };

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