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sys/contrib/device-tree/Bindings/mtd/atmel-nand.txt
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1 Atmel NAND flash controller bindings 2 3 The NAND flash controller node should be defined under the EBI bus (see 4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt). 5 One or several NAND devices can be defined under this NAND controller. 6 The NAND controller might be connected to an ECC engine. 7 8 * NAND controller bindings: 9 10 Required properties: 11 - compatible: should be one of the following 12 "atmel,at91rm9200-nand-controller" 13 "atmel,at91sam9260-nand-controller" 14 "atmel,at91sam9261-nand-controller" 15 "atmel,at91sam9g45-nand-controller" 16 "atmel,sama5d3-nand-controller" 17 "microchip,sam9x60-nand-controller" 18 - ranges: empty ranges property to forward EBI ranges definitions. 19 - #address-cells: should be set to 2. 20 - #size-cells: should be set to 1. 21 - atmel,nfc-io: phandle to the NFC IO block. Only required for sama5d3 22 controllers. 23 - atmel,nfc-sram: phandle to the NFC SRAM block. Only required for sama5d3 24 controllers. 25 26 Optional properties: 27 - ecc-engine: phandle to the PMECC block. Only meaningful if the SoC embeds 28 a PMECC engine. 29 30 * NAND device/chip bindings: 31 32 Required properties: 33 - reg: describes the CS lines assigned to the NAND device. If the NAND device 34 exposes multiple CS lines (multi-dies chips), your reg property will 35 contain X tuples of 3 entries. 36 1st entry: the CS line this NAND chip is connected to 37 2nd entry: the base offset of the memory region assigned to this 38 device (always 0) 39 3rd entry: the memory region size (always 0x800000) 40 41 Optional properties: 42 - rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND. 43 - cs-gpios: the GPIO(s) used to control the CS line. 44 - det-gpios: the GPIO used to detect if a Smartmedia Card is present. 45 - atmel,rb: an integer identifying the native Ready/Busy pin. Only meaningful 46 on sama5 SoCs. 47 48 All generic properties described in 49 Documentation/devicetree/bindings/mtd/{common,nand}.txt also apply to the NAND 50 device node, and NAND partitions should be defined under the NAND node as 51 described in Documentation/devicetree/bindings/mtd/partition.txt. 52 53 * ECC engine (PMECC) bindings: 54 55 Required properties: 56 - compatible: should be one of the following 57 "atmel,at91sam9g45-pmecc" 58 "atmel,sama5d4-pmecc" 59 "atmel,sama5d2-pmecc" 60 "microchip,sam9x60-pmecc" 61 - reg: should contain 2 register ranges. The first one is pointing to the PMECC 62 block, and the second one to the PMECC_ERRLOC block. 63 64 * SAMA5 NFC I/O bindings: 65 66 SAMA5 SoCs embed an advanced NAND controller logic to automate READ/WRITE page 67 operations. This interface to this logic is placed in a separate I/O range and 68 should thus have its own DT node. 69 70 - compatible: should be "atmel,sama5d3-nfc-io", "syscon". 71 - reg: should contain the I/O range used to interact with the NFC logic. 72 73 Example: 74 75 nfc_io: nfc-io@70000000 { 76 compatible = "atmel,sama5d3-nfc-io", "syscon"; 77 reg = <0x70000000 0x8000000>; 78 }; 79 80 pmecc: ecc-engine@ffffc070 { 81 compatible = "atmel,at91sam9g45-pmecc"; 82 reg = <0xffffc070 0x490>, 83 <0xffffc500 0x100>; 84 }; 85 86 ebi: ebi@10000000 { 87 compatible = "atmel,sama5d3-ebi"; 88 #address-cells = <2>; 89 #size-cells = <1>; 90 atmel,smc = <&hsmc>; 91 reg = <0x10000000 0x10000000 92 0x40000000 0x30000000>; 93 ranges = <0x0 0x0 0x10000000 0x10000000 94 0x1 0x0 0x40000000 0x10000000 95 0x2 0x0 0x50000000 0x10000000 96 0x3 0x0 0x60000000 0x10000000>; 97 clocks = <&mck>; 98 99 nand_controller: nand-controller { 100 compatible = "atmel,sama5d3-nand-controller"; 101 atmel,nfc-sram = <&nfc_sram>; 102 atmel,nfc-io = <&nfc_io>; 103 ecc-engine = <&pmecc>; 104 #address-cells = <2>; 105 #size-cells = <1>; 106 ranges; 107 108 nand@3 { 109 reg = <0x3 0x0 0x800000>; 110 atmel,rb = <0>; 111 112 /* 113 * Put generic NAND/MTD properties and 114 * subnodes here. 115 */ 116 }; 117 }; 118 }; 119 120 ----------------------------------------------------------------------- 121 122 Deprecated bindings (should not be used in new device trees): 123 124 Required properties: 125 - compatible: The possible values are: 126 "atmel,at91rm9200-nand" 127 "atmel,sama5d2-nand" 128 "atmel,sama5d4-nand" 129 - reg : should specify localbus address and size used for the chip, 130 and hardware ECC controller if available. 131 If the hardware ECC is PMECC, it should contain address and size for 132 PMECC and PMECC Error Location controller. 133 The PMECC lookup table address and size in ROM is optional. If not 134 specified, driver will build it in runtime. 135 - atmel,nand-addr-offset : offset for the address latch. 136 - atmel,nand-cmd-offset : offset for the command latch. 137 - #address-cells, #size-cells : Must be present if the device has sub-nodes 138 representing partitions. 139 140 - gpios : specifies the gpio pins to control the NAND device. detect is an 141 optional gpio and may be set to 0 if not present. 142 143 Optional properties: 144 - atmel,nand-has-dma : boolean to support dma transfer for nand read/write. 145 - nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default. 146 Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first", 147 "soft_bch". 148 - atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware, 149 capable of BCH encoding and decoding, on devices where it is present. 150 - atmel,pmecc-cap : error correct capability for Programmable Multibit ECC 151 Controller. Supported values are: 2, 4, 8, 12, 24. If the compatible string 152 is "atmel,sama5d2-nand", 32 is also valid. 153 - atmel,pmecc-sector-size : sector size for ECC computation. Supported values 154 are: 512, 1024. 155 - atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM 156 for different sector size. First one is for sector size 512, the next is for 157 sector size 1024. If not specified, driver will build the table in runtime. 158 - nand-bus-width : 8 or 16 bus width if not present 8 159 - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false 160 161 Nand Flash Controller(NFC) is an optional sub-node 162 Required properties: 163 - compatible : "atmel,sama5d3-nfc". 164 - reg : should specify the address and size used for NFC command registers, 165 NFC registers and NFC SRAM. NFC SRAM address and size can be absent 166 if don't want to use it. 167 - clocks: phandle to the peripheral clock 168 Optional properties: 169 - atmel,write-by-sram: boolean to enable NFC write by SRAM. 170 171 Examples: 172 nand0: nand@40000000,0 { 173 compatible = "atmel,at91rm9200-nand"; 174 #address-cells = <1>; 175 #size-cells = <1>; 176 reg = <0x40000000 0x10000000 177 0xffffe800 0x200 178 >; 179 atmel,nand-addr-offset = <21>; /* ale */ 180 atmel,nand-cmd-offset = <22>; /* cle */ 181 nand-on-flash-bbt; 182 nand-ecc-mode = "soft"; 183 gpios = <&pioC 13 0 /* rdy */ 184 &pioC 14 0 /* nce */ 185 0 /* cd */ 186 >; 187 partition@0 { 188 ... 189 }; 190 }; 191 192 /* for PMECC supported chips */ 193 nand0: nand@40000000 { 194 compatible = "atmel,at91rm9200-nand"; 195 #address-cells = <1>; 196 #size-cells = <1>; 197 reg = < 0x40000000 0x10000000 /* bus addr & size */ 198 0xffffe000 0x00000600 /* PMECC addr & size */ 199 0xffffe600 0x00000200 /* PMECC ERRLOC addr & size */ 200 0x00100000 0x00100000 /* ROM addr & size */ 201 >; 202 atmel,nand-addr-offset = <21>; /* ale */ 203 atmel,nand-cmd-offset = <22>; /* cle */ 204 nand-on-flash-bbt; 205 nand-ecc-mode = "hw"; 206 atmel,has-pmecc; /* enable PMECC */ 207 atmel,pmecc-cap = <2>; 208 atmel,pmecc-sector-size = <512>; 209 atmel,pmecc-lookup-table-offset = <0x8000 0x10000>; 210 gpios = <&pioD 5 0 /* rdy */ 211 &pioD 4 0 /* nce */ 212 0 /* cd */ 213 >; 214 partition@0 { 215 ... 216 }; 217 }; 218 219 /* for NFC supported chips */ 220 nand0: nand@40000000 { 221 compatible = "atmel,at91rm9200-nand"; 222 #address-cells = <1>; 223 #size-cells = <1>; 224 ranges; 225 ... 226 nfc@70000000 { 227 compatible = "atmel,sama5d3-nfc"; 228 #address-cells = <1>; 229 #size-cells = <1>; 230 clocks = <&hsmc_clk> 231 reg = < 232 0x70000000 0x10000000 /* NFC Command Registers */ 233 0xffffc000 0x00000070 /* NFC HSMC regs */ 234 0x00200000 0x00100000 /* NFC SRAM banks */ 235 >; 236 }; 237 };
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