The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/mtd/cadence-quadspi.txt

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    1 * Cadence Quad SPI controller
    2 
    3 Required properties:
    4 - compatible : should be one of the following:
    5         Generic default - "cdns,qspi-nor".
    6         For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
    7         For TI AM654 SoC  - "ti,am654-ospi", "cdns,qspi-nor".
    8 - reg : Contains two entries, each of which is a tuple consisting of a
    9         physical address and length. The first entry is the address and
   10         length of the controller register set. The second entry is the
   11         address and length of the QSPI Controller data area.
   12 - interrupts : Unit interrupt specifier for the controller interrupt.
   13 - clocks : phandle to the Quad SPI clock.
   14 - cdns,fifo-depth : Size of the data FIFO in words.
   15 - cdns,fifo-width : Bus width of the data FIFO in bytes.
   16 - cdns,trigger-address : 32-bit indirect AHB trigger address.
   17 
   18 Optional properties:
   19 - cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
   20 - cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch
   21   the read data rather than the QSPI clock. Make sure that QSPI return
   22   clock is populated on the board before using this property.
   23 
   24 Optional subnodes:
   25 Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional
   26 custom properties:
   27 - cdns,read-delay : Delay for read capture logic, in clock cycles
   28 - cdns,tshsl-ns : Delay in nanoseconds for the length that the master
   29                   mode chip select outputs are de-asserted between
   30                   transactions.
   31 - cdns,tsd2d-ns : Delay in nanoseconds between one chip select being
   32                   de-activated and the activation of another.
   33 - cdns,tchsh-ns : Delay in nanoseconds between last bit of current
   34                   transaction and deasserting the device chip select
   35                   (qspi_n_ss_out).
   36 - cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low
   37                   and first bit transfer.
   38 - resets        : Must contain an entry for each entry in reset-names.
   39                   See ../reset/reset.txt for details.
   40 - reset-names   : Must include either "qspi" and/or "qspi-ocp".
   41 
   42 Example:
   43 
   44         qspi: spi@ff705000 {
   45                 compatible = "cdns,qspi-nor";
   46                 #address-cells = <1>;
   47                 #size-cells = <0>;
   48                 reg = <0xff705000 0x1000>,
   49                       <0xffa00000 0x1000>;
   50                 interrupts = <0 151 4>;
   51                 clocks = <&qspi_clk>;
   52                 cdns,is-decoded-cs;
   53                 cdns,fifo-depth = <128>;
   54                 cdns,fifo-width = <4>;
   55                 cdns,trigger-address = <0x00000000>;
   56                 resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
   57                 reset-names = "qspi", "qspi-ocp";
   58 
   59                 flash0: n25q00@0 {
   60                         ...
   61                         cdns,read-delay = <4>;
   62                         cdns,tshsl-ns = <50>;
   63                         cdns,tsd2d-ns = <50>;
   64                         cdns,tchsh-ns = <4>;
   65                         cdns,tslch-ns = <4>;
   66                 };
   67         };

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