FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/mtd/nand-controller.yaml

     # SPDX-License-Identifier: GPL-2.0
     %YAML 1.2
     ---
     $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
     $schema: http://devicetree.org/meta-schemas/core.yaml#
     
     title: NAND Chip and NAND Controller Generic Binding
     
     maintainers:
      - Miquel Raynal <miquel.raynal@bootlin.com>
      - Richard Weinberger <richard@nod.at>
    
    description: |
      The NAND controller should be represented with its own DT node, and
      all NAND chips attached to this controller should be defined as
      children nodes of the NAND controller. This representation should be
      enforced even for simple controllers supporting only one chip.
    
      The ECC strength and ECC step size properties define the user
      desires in terms of correction capability of a controller. Together,
      they request the ECC engine to correct {strength} bit errors per
      {size} bytes.
    
      The interpretation of these parameters is implementation-defined, so
      not all implementations must support all possible
      combinations. However, implementations are encouraged to further
      specify the value(s) they support.
    
    properties:
      $nodename:
        pattern: "^nand-controller(@.*)?"
    
      "#address-cells":
        const: 1
    
      "#size-cells":
        const: 0
    
      ranges: true
    
      cs-gpios:
        description:
          Array of chip-select available to the controller. The first
          entries are a 1:1 mapping of the available chip-select on the
          NAND controller (even if they are not used). As many additional
          chip-select as needed may follow and should be phandles of GPIO
          lines. 'reg' entries of the NAND chip subnodes become indexes of
          this array when this property is present.
        minItems: 1
        maxItems: 8
    
    patternProperties:
      "^nand@[a-f0-9]$":
        type: object
        $ref: "nand-chip.yaml#"
    
        properties:
          reg:
            description:
              Contains the chip-select IDs.
    
          nand-ecc-placement:
            description:
              Location of the ECC bytes. This location is unknown by default
              but can be explicitly set to "oob", if all ECC bytes are
              known to be stored in the OOB area, or "interleaved" if ECC
              bytes will be interleaved with regular data in the main area.
            $ref: /schemas/types.yaml#/definitions/string
            enum: [ oob, interleaved ]
    
          nand-bus-width:
            description:
              Bus width to the NAND chip
            $ref: /schemas/types.yaml#/definitions/uint32
            enum: [8, 16]
            default: 8
    
          nand-on-flash-bbt:
            description:
              With this property, the OS will search the device for a Bad
              Block Table (BBT). If not found, it will create one, reserve
              a few blocks at the end of the device to store it and update
              it as the device ages. Otherwise, the out-of-band area of a
              few pages of all the blocks will be scanned at boot time to
              find Bad Block Markers (BBM). These markers will help to
              build a volatile BBT in RAM.
            $ref: /schemas/types.yaml#/definitions/flag
    
          nand-ecc-maximize:
            description:
              Whether or not the ECC strength should be maximized. The
              maximum ECC strength is both controller and chip
              dependent. The ECC engine has to select the ECC config
              providing the best strength and taking the OOB area size
              constraint into account. This is particularly useful when
              only the in-band area is used by the upper layers, and you
              want to make your NAND as reliable as possible.
            $ref: /schemas/types.yaml#/definitions/flag
    
         nand-is-boot-medium:
           description:
             Whether or not the NAND chip is a boot medium. Drivers might
             use this information to select ECC algorithms supported by
             the boot ROM or similar restrictions.
           $ref: /schemas/types.yaml#/definitions/flag
   
         nand-rb:
           description:
             Contains the native Ready/Busy IDs.
           $ref: /schemas/types.yaml#/definitions/uint32-array
   
         rb-gpios:
           description:
             Contains one or more GPIO descriptor (the numper of descriptor
             depends on the number of R/B pins exposed by the flash) for the
             Ready/Busy pins. Active state refers to the NAND ready state and
             should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
   
         wp-gpios:
           description:
             Contains one GPIO descriptor for the Write Protect pin.
             Active state refers to the NAND Write Protect state and should be
             set to GPIOD_ACTIVE_LOW unless the signal is inverted.
           maxItems: 1
   
       required:
         - reg
   
   required:
     - "#address-cells"
     - "#size-cells"
   
   additionalProperties: true
   
   examples:
     - |
       nand-controller {
         #address-cells = <1>;
         #size-cells = <0>;
         cs-gpios = <0>, <&gpioA 1>; /* A single native CS is available */
   
         /* controller specific properties */
   
         nand@0 {
           reg = <0>; /* Native CS */
           /* NAND chip specific properties */
         };
   
         nand@1 {
           reg = <1>; /* GPIO CS */
         };
       };

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