The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)

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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/mux/reg-mux.txt

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    1 Generic register bitfield-based multiplexer controller bindings
    2 
    3 Define register bitfields to be used to control multiplexers. The parent
    4 device tree node must be a device node to provide register r/w access.
    5 
    6 Required properties:
    7 - compatible : should be one of
    8         "reg-mux" : if parent device of mux controller is not syscon device
    9         "mmio-mux" : if parent device of mux controller is syscon device
   10 - #mux-control-cells : <1>
   11 - mux-reg-masks : an array of register offset and pre-shifted bitfield mask
   12                   pairs, each describing a single mux control.
   13 * Standard mux-controller bindings as decribed in mux-controller.txt
   14 
   15 Optional properties:
   16 - idle-states : if present, the state the muxes will have when idle. The
   17                 special state MUX_IDLE_AS_IS is the default.
   18 
   19 The multiplexer state of each multiplexer is defined as the value of the
   20 bitfield described by the corresponding register offset and bitfield mask
   21 pair in the mux-reg-masks array.
   22 
   23 Example 1:
   24 The parent device of mux controller is not a syscon device.
   25 
   26 &i2c0 {
   27         fpga@66 { // fpga connected to i2c
   28                 compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
   29                              "simple-mfd";
   30                 reg = <0x66>;
   31 
   32                 mux: mux-controller {
   33                         compatible = "reg-mux";
   34                         #mux-control-cells = <1>;
   35                         mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
   36                                         <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */
   37                 };
   38         };
   39 };
   40 
   41 mdio-mux-1 {
   42         compatible = "mdio-mux-multiplexer";
   43         mux-controls = <&mux 0>;
   44         mdio-parent-bus = <&emdio1>;
   45         #address-cells = <1>;
   46         #size-cells = <0>;
   47 
   48         mdio@0 {
   49                 reg = <0x0>;
   50                 #address-cells = <1>;
   51                 #size-cells = <0>;
   52         };
   53 
   54         mdio@8 {
   55                 reg = <0x8>;
   56                 #address-cells = <1>;
   57                 #size-cells = <0>;
   58         };
   59 
   60         ..
   61         ..
   62 };
   63 
   64 mdio-mux-2 {
   65         compatible = "mdio-mux-multiplexer";
   66         mux-controls = <&mux 1>;
   67         mdio-parent-bus = <&emdio2>;
   68         #address-cells = <1>;
   69         #size-cells = <0>;
   70 
   71         mdio@0 {
   72                 reg = <0x0>;
   73                 #address-cells = <1>;
   74                 #size-cells = <0>;
   75         };
   76 
   77         mdio@1 {
   78                 reg = <0x1>;
   79                 #address-cells = <1>;
   80                 #size-cells = <0>;
   81         };
   82 
   83         ..
   84         ..
   85 };
   86 
   87 Example 2:
   88 The parent device of mux controller is syscon device.
   89 
   90 syscon {
   91         compatible = "syscon";
   92 
   93         mux: mux-controller {
   94                 compatible = "mmio-mux";
   95                 #mux-control-cells = <1>;
   96 
   97                 mux-reg-masks = <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */
   98                                 <0x3 0x40>, /* 1: reg 0x3, bit 6 */
   99                 idle-states = <MUX_IDLE_AS_IS>, <0>;
  100         };
  101 };
  102 
  103 video-mux {
  104         compatible = "video-mux";
  105         mux-controls = <&mux 0>;
  106         #address-cells = <1>;
  107         #size-cells = <0>;
  108 
  109         ports {
  110                 /* inputs 0..3 */
  111                 port@0 {
  112                         reg = <0>;
  113                 };
  114                 port@1 {
  115                         reg = <1>;
  116                 };
  117                 port@2 {
  118                         reg = <2>;
  119                 };
  120                 port@3 {
  121                         reg = <3>;
  122                 };
  123 
  124                 /* output */
  125                 port@4 {
  126                         reg = <4>;
  127                 };
  128         };
  129 };

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