The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/net/ethernet-phy.yaml

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    1 # SPDX-License-Identifier: GPL-2.0
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Ethernet PHY Generic Binding
    8 
    9 maintainers:
   10   - Andrew Lunn <andrew@lunn.ch>
   11   - Florian Fainelli <f.fainelli@gmail.com>
   12   - Heiner Kallweit <hkallweit1@gmail.com>
   13 
   14 # The dt-schema tools will generate a select statement first by using
   15 # the compatible, and second by using the node name if any. In our
   16 # case, the node name is the one we want to match on, while the
   17 # compatible is optional.
   18 select:
   19   properties:
   20     $nodename:
   21       pattern: "^ethernet-phy(@[a-f0-9]+)?$"
   22 
   23   required:
   24     - $nodename
   25 
   26 properties:
   27   $nodename:
   28     pattern: "^ethernet-phy(@[a-f0-9]+)?$"
   29 
   30   compatible:
   31     oneOf:
   32       - const: ethernet-phy-ieee802.3-c22
   33         description: PHYs that implement IEEE802.3 clause 22
   34       - const: ethernet-phy-ieee802.3-c45
   35         description: PHYs that implement IEEE802.3 clause 45
   36       - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
   37         description:
   38           If the PHY reports an incorrect ID (or none at all) then the
   39           compatible list may contain an entry with the correct PHY ID
   40           in the above form.
   41           The first group of digits is the 16 bit Phy Identifier 1
   42           register, this is the chip vendor OUI bits 3:18. The
   43           second group of digits is the Phy Identifier 2 register,
   44           this is the chip vendor OUI bits 19:24, followed by 10
   45           bits of a vendor specific ID.
   46       - items:
   47           - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
   48           - const: ethernet-phy-ieee802.3-c22
   49       - items:
   50           - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
   51           - const: ethernet-phy-ieee802.3-c45
   52 
   53   reg:
   54     minimum: 0
   55     maximum: 31
   56     description:
   57       The ID number for the PHY.
   58 
   59   interrupts:
   60     maxItems: 1
   61 
   62   max-speed:
   63     enum:
   64       - 10
   65       - 100
   66       - 1000
   67       - 2500
   68       - 5000
   69       - 10000
   70       - 20000
   71       - 25000
   72       - 40000
   73       - 50000
   74       - 56000
   75       - 100000
   76       - 200000
   77     description:
   78       Maximum PHY supported speed in Mbits / seconds.
   79 
   80   phy-10base-t1l-2.4vpp:
   81     description: |
   82       tristate, request/disable 2.4 Vpp operating mode. The values are:
   83       0: Disable 2.4 Vpp operating mode.
   84       1: Request 2.4 Vpp operating mode from link partner.
   85       Absence of this property will leave configuration to default values.
   86     $ref: "/schemas/types.yaml#/definitions/uint32"
   87     enum: [0, 1]
   88 
   89   broken-turn-around:
   90     $ref: /schemas/types.yaml#/definitions/flag
   91     description:
   92       If set, indicates the PHY device does not correctly release
   93       the turn around line low at end of the control phase of the
   94       MDIO transaction.
   95 
   96   enet-phy-lane-swap:
   97     $ref: /schemas/types.yaml#/definitions/flag
   98     description:
   99       If set, indicates the PHY will swap the TX/RX lanes to
  100       compensate for the board being designed with the lanes
  101       swapped.
  102 
  103   enet-phy-lane-no-swap:
  104     $ref: /schemas/types.yaml#/definitions/flag
  105     description:
  106       If set, indicates that PHY will disable swap of the
  107       TX/RX lanes. This property allows the PHY to work correcly after
  108       e.g. wrong bootstrap configuration caused by issues in PCB
  109       layout design.
  110 
  111   eee-broken-100tx:
  112     $ref: /schemas/types.yaml#/definitions/flag
  113     description:
  114       Mark the corresponding energy efficient ethernet mode as
  115       broken and request the ethernet to stop advertising it.
  116 
  117   eee-broken-1000t:
  118     $ref: /schemas/types.yaml#/definitions/flag
  119     description:
  120       Mark the corresponding energy efficient ethernet mode as
  121       broken and request the ethernet to stop advertising it.
  122 
  123   eee-broken-10gt:
  124     $ref: /schemas/types.yaml#/definitions/flag
  125     description:
  126       Mark the corresponding energy efficient ethernet mode as
  127       broken and request the ethernet to stop advertising it.
  128 
  129   eee-broken-1000kx:
  130     $ref: /schemas/types.yaml#/definitions/flag
  131     description:
  132       Mark the corresponding energy efficient ethernet mode as
  133       broken and request the ethernet to stop advertising it.
  134 
  135   eee-broken-10gkx4:
  136     $ref: /schemas/types.yaml#/definitions/flag
  137     description:
  138       Mark the corresponding energy efficient ethernet mode as
  139       broken and request the ethernet to stop advertising it.
  140 
  141   eee-broken-10gkr:
  142     $ref: /schemas/types.yaml#/definitions/flag
  143     description:
  144       Mark the corresponding energy efficient ethernet mode as
  145       broken and request the ethernet to stop advertising it.
  146 
  147   phy-is-integrated:
  148     $ref: /schemas/types.yaml#/definitions/flag
  149     description:
  150       If set, indicates that the PHY is integrated into the same
  151       physical package as the Ethernet MAC. If needed, muxers
  152       should be configured to ensure the integrated PHY is
  153       used. The absence of this property indicates the muxers
  154       should be configured so that the external PHY is used.
  155 
  156   resets:
  157     maxItems: 1
  158 
  159   reset-names:
  160     const: phy
  161 
  162   reset-gpios:
  163     maxItems: 1
  164     description:
  165       The GPIO phandle and specifier for the PHY reset signal.
  166 
  167   reset-assert-us:
  168     description:
  169       Delay after the reset was asserted in microseconds. If this
  170       property is missing the delay will be skipped.
  171 
  172   reset-deassert-us:
  173     description:
  174       Delay after the reset was deasserted in microseconds. If
  175       this property is missing the delay will be skipped.
  176 
  177   sfp:
  178     $ref: /schemas/types.yaml#/definitions/phandle
  179     description:
  180       Specifies a reference to a node representing a SFP cage.
  181 
  182   rx-internal-delay-ps:
  183     description: |
  184       RGMII Receive PHY Clock Delay defined in pico seconds.  This is used for
  185       PHY's that have configurable RX internal delays.  If this property is
  186       present then the PHY applies the RX delay.
  187 
  188   tx-internal-delay-ps:
  189     description: |
  190       RGMII Transmit PHY Clock Delay defined in pico seconds.  This is used for
  191       PHY's that have configurable TX internal delays. If this property is
  192       present then the PHY applies the TX delay.
  193 
  194 required:
  195   - reg
  196 
  197 additionalProperties: true
  198 
  199 examples:
  200   - |
  201     ethernet {
  202         #address-cells = <1>;
  203         #size-cells = <0>;
  204 
  205         ethernet-phy@0 {
  206             compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c45";
  207             interrupt-parent = <&PIC>;
  208             interrupts = <35 1>;
  209             reg = <0>;
  210 
  211             resets = <&rst 8>;
  212             reset-names = "phy";
  213             reset-gpios = <&gpio1 4 1>;
  214             reset-assert-us = <1000>;
  215             reset-deassert-us = <2000>;
  216         };
  217     };

Cache object: f04a09ad70c9b67a948dcdcbc257ce60


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