mdio-mux.txt

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    1 Common MDIO bus multiplexer/switch properties.
    2 
    3 An MDIO bus multiplexer/switch will have several child busses that are
    4 numbered uniquely in a device dependent manner.  The nodes for an MDIO
    5 bus multiplexer/switch will have one child node for each child bus.
    6 
    7 Required properties:
    8 - #address-cells = <1>;
    9 - #size-cells = <0>;
   10 
   11 Optional properties:
   12 - mdio-parent-bus : phandle to the parent MDIO bus.
   13 
   14 - Other properties specific to the multiplexer/switch hardware.
   15 
   16 Required properties for child nodes:
   17 - #address-cells = <1>;
   18 - #size-cells = <0>;
   19 - reg : The sub-bus number.
   20 
   21 
   22 Example :
   23 
   24         /* The parent MDIO bus. */
   25         smi1: mdio@1180000001900 {
   26                 compatible = "cavium,octeon-3860-mdio";
   27                 #address-cells = <1>;
   28                 #size-cells = <0>;
   29                 reg = <0x11800 0x00001900 0x0 0x40>;
   30         };
   31 
   32         /*
   33            An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
   34            pair of GPIO lines.  Child busses 2 and 3 populated with 4
   35            PHYs each.
   36          */
   37         mdio-mux {
   38                 compatible = "mdio-mux-gpio";
   39                 gpios = <&gpio1 3 0>, <&gpio1 4 0>;
   40                 mdio-parent-bus = <&smi1>;
   41                 #address-cells = <1>;
   42                 #size-cells = <0>;
   43 
   44                 mdio@2 {
   45                         reg = <2>;
   46                         #address-cells = <1>;
   47                         #size-cells = <0>;
   48 
   49                         phy11: ethernet-phy@1 {
   50                                 reg = <1>;
   51                                 marvell,reg-init = <3 0x10 0 0x5777>,
   52                                         <3 0x11 0 0x00aa>,
   53                                         <3 0x12 0 0x4105>,
   54                                         <3 0x13 0 0x0a60>;
   55                                 interrupt-parent = <&gpio>;
   56                                 interrupts = <10 8>; /* Pin 10, active low */
   57                         };
   58                         phy12: ethernet-phy@2 {
   59                                 reg = <2>;
   60                                 marvell,reg-init = <3 0x10 0 0x5777>,
   61                                         <3 0x11 0 0x00aa>,
   62                                         <3 0x12 0 0x4105>,
   63                                         <3 0x13 0 0x0a60>;
   64                                 interrupt-parent = <&gpio>;
   65                                 interrupts = <10 8>; /* Pin 10, active low */
   66                         };
   67                         phy13: ethernet-phy@3 {
   68                                 reg = <3>;
   69                                 marvell,reg-init = <3 0x10 0 0x5777>,
   70                                         <3 0x11 0 0x00aa>,
   71                                         <3 0x12 0 0x4105>,
   72                                         <3 0x13 0 0x0a60>;
   73                                 interrupt-parent = <&gpio>;
   74                                 interrupts = <10 8>; /* Pin 10, active low */
   75                         };
   76                         phy14: ethernet-phy@4 {
   77                                 reg = <4>;
   78                                 marvell,reg-init = <3 0x10 0 0x5777>,
   79                                         <3 0x11 0 0x00aa>,
   80                                         <3 0x12 0 0x4105>,
   81                                         <3 0x13 0 0x0a60>;
   82                                 interrupt-parent = <&gpio>;
   83                                 interrupts = <10 8>; /* Pin 10, active low */
   84                         };
   85                 };
   86 
   87                 mdio@3 {
   88                         reg = <3>;
   89                         #address-cells = <1>;
   90                         #size-cells = <0>;
   91 
   92                         phy21: ethernet-phy@1 {
   93                                 reg = <1>;
   94                                 marvell,reg-init = <3 0x10 0 0x5777>,
   95                                         <3 0x11 0 0x00aa>,
   96                                         <3 0x12 0 0x4105>,
   97                                         <3 0x13 0 0x0a60>;
   98                                 interrupt-parent = <&gpio>;
   99                                 interrupts = <12 8>; /* Pin 12, active low */
  100                         };
  101                         phy22: ethernet-phy@2 {
  102                                 reg = <2>;
  103                                 marvell,reg-init = <3 0x10 0 0x5777>,
  104                                         <3 0x11 0 0x00aa>,
  105                                         <3 0x12 0 0x4105>,
  106                                         <3 0x13 0 0x0a60>;
  107                                 interrupt-parent = <&gpio>;
  108                                 interrupts = <12 8>; /* Pin 12, active low */
  109                         };
  110                         phy23: ethernet-phy@3 {
  111                                 reg = <3>;
  112                                 marvell,reg-init = <3 0x10 0 0x5777>,
  113                                         <3 0x11 0 0x00aa>,
  114                                         <3 0x12 0 0x4105>,
  115                                         <3 0x13 0 0x0a60>;
  116                                 interrupt-parent = <&gpio>;
  117                                 interrupts = <12 8>; /* Pin 12, active low */
  118                         };
  119                         phy24: ethernet-phy@4 {
  120                                 reg = <4>;
  121                                 marvell,reg-init = <3 0x10 0 0x5777>,
  122                                         <3 0x11 0 0x00aa>,
  123                                         <3 0x12 0 0x4105>,
  124                                         <3 0x13 0 0x0a60>;
  125                                 interrupt-parent = <&gpio>;
  126                                 interrupts = <12 8>; /* Pin 12, active low */
  127                         };
  128                 };
  129         };

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