mediatek,net.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/net/mediatek,net.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: MediaTek Frame Engine Ethernet controller
    8 
    9 maintainers:
   10   - Lorenzo Bianconi <lorenzo@kernel.org>
   11   - Felix Fietkau <nbd@nbd.name>
   12 
   13 description:
   14   The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
   15   have dual GMAC ports.
   16 
   17 properties:
   18   compatible:
   19     enum:
   20       - mediatek,mt2701-eth
   21       - mediatek,mt7623-eth
   22       - mediatek,mt7622-eth
   23       - mediatek,mt7629-eth
   24       - mediatek,mt7986-eth
   25       - ralink,rt5350-eth
   26 
   27   reg:
   28     maxItems: 1
   29 
   30   clocks: true
   31   clock-names: true
   32 
   33   interrupts:
   34     minItems: 3
   35     maxItems: 4
   36 
   37   power-domains:
   38     maxItems: 1
   39 
   40   resets:
   41     maxItems: 3
   42 
   43   reset-names:
   44     items:
   45       - const: fe
   46       - const: gmac
   47       - const: ppe
   48 
   49   mediatek,ethsys:
   50     $ref: /schemas/types.yaml#/definitions/phandle
   51     description:
   52       Phandle to the syscon node that handles the port setup.
   53 
   54   cci-control-port: true
   55 
   56   mediatek,hifsys:
   57     $ref: /schemas/types.yaml#/definitions/phandle
   58     description:
   59       Phandle to the mediatek hifsys controller used to provide various clocks
   60       and reset to the system.
   61 
   62   mediatek,sgmiisys:
   63     $ref: /schemas/types.yaml#/definitions/phandle-array
   64     minItems: 1
   65     maxItems: 2
   66     items:
   67       maxItems: 1
   68     description:
   69       A list of phandle to the syscon node that handles the SGMII setup which is required for
   70       those SoCs equipped with SGMII.
   71 
   72   dma-coherent: true
   73 
   74   mdio-bus:
   75     $ref: mdio.yaml#
   76     unevaluatedProperties: false
   77 
   78   "#address-cells":
   79     const: 1
   80 
   81   "#size-cells":
   82     const: 0
   83 
   84 allOf:
   85   - $ref: "ethernet-controller.yaml#"
   86   - if:
   87       properties:
   88         compatible:
   89           contains:
   90             enum:
   91               - mediatek,mt2701-eth
   92               - mediatek,mt7623-eth
   93     then:
   94       properties:
   95         interrupts:
   96           maxItems: 3
   97 
   98         clocks:
   99           minItems: 4
  100           maxItems: 4
  101 
  102         clock-names:
  103           items:
  104             - const: ethif
  105             - const: esw
  106             - const: gp1
  107             - const: gp2
  108 
  109         mediatek,pctl:
  110           $ref: /schemas/types.yaml#/definitions/phandle
  111           description:
  112             Phandle to the syscon node that handles the ports slew rate and
  113             driver current.
  114 
  115   - if:
  116       properties:
  117         compatible:
  118           contains:
  119             const: mediatek,mt7622-eth
  120     then:
  121       properties:
  122         interrupts:
  123           maxItems: 3
  124 
  125         clocks:
  126           minItems: 11
  127           maxItems: 11
  128 
  129         clock-names:
  130           items:
  131             - const: ethif
  132             - const: esw
  133             - const: gp0
  134             - const: gp1
  135             - const: gp2
  136             - const: sgmii_tx250m
  137             - const: sgmii_rx250m
  138             - const: sgmii_cdr_ref
  139             - const: sgmii_cdr_fb
  140             - const: sgmii_ck
  141             - const: eth2pll
  142 
  143         mediatek,sgmiisys:
  144           minItems: 1
  145           maxItems: 1
  146 
  147         mediatek,wed:
  148           $ref: /schemas/types.yaml#/definitions/phandle-array
  149           minItems: 2
  150           maxItems: 2
  151           items:
  152             maxItems: 1
  153           description:
  154             List of phandles to wireless ethernet dispatch nodes.
  155 
  156         mediatek,pcie-mirror:
  157           $ref: /schemas/types.yaml#/definitions/phandle
  158           description:
  159             Phandle to the mediatek pcie-mirror controller.
  160 
  161   - if:
  162       properties:
  163         compatible:
  164           contains:
  165             const: mediatek,mt7629-eth
  166     then:
  167       properties:
  168         interrupts:
  169           maxItems: 3
  170 
  171         clocks:
  172           minItems: 17
  173           maxItems: 17
  174 
  175         clock-names:
  176           items:
  177             - const: ethif
  178             - const: sgmiitop
  179             - const: esw
  180             - const: gp0
  181             - const: gp1
  182             - const: gp2
  183             - const: fe
  184             - const: sgmii_tx250m
  185             - const: sgmii_rx250m
  186             - const: sgmii_cdr_ref
  187             - const: sgmii_cdr_fb
  188             - const: sgmii2_tx250m
  189             - const: sgmii2_rx250m
  190             - const: sgmii2_cdr_ref
  191             - const: sgmii2_cdr_fb
  192             - const: sgmii_ck
  193             - const: eth2pll
  194 
  195         mediatek,infracfg:
  196           $ref: /schemas/types.yaml#/definitions/phandle
  197           description:
  198             Phandle to the syscon node that handles the path from GMAC to
  199             PHY variants.
  200 
  201         mediatek,sgmiisys:
  202           minItems: 2
  203           maxItems: 2
  204 
  205   - if:
  206       properties:
  207         compatible:
  208           contains:
  209             const: mediatek,mt7986-eth
  210     then:
  211       properties:
  212         interrupts:
  213           minItems: 4
  214 
  215         clocks:
  216           minItems: 15
  217           maxItems: 15
  218 
  219         clock-names:
  220           items:
  221             - const: fe
  222             - const: gp2
  223             - const: gp1
  224             - const: wocpu1
  225             - const: wocpu0
  226             - const: sgmii_tx250m
  227             - const: sgmii_rx250m
  228             - const: sgmii_cdr_ref
  229             - const: sgmii_cdr_fb
  230             - const: sgmii2_tx250m
  231             - const: sgmii2_rx250m
  232             - const: sgmii2_cdr_ref
  233             - const: sgmii2_cdr_fb
  234             - const: netsys0
  235             - const: netsys1
  236 
  237         mediatek,sgmiisys:
  238           minItems: 2
  239           maxItems: 2
  240 
  241 patternProperties:
  242   "^mac@[0-1]$":
  243     type: object
  244     additionalProperties: false
  245     allOf:
  246       - $ref: ethernet-controller.yaml#
  247     description:
  248       Ethernet MAC node
  249     properties:
  250       compatible:
  251         const: mediatek,eth-mac
  252 
  253       reg:
  254         maxItems: 1
  255 
  256       phy-handle: true
  257 
  258       phy-mode: true
  259 
  260     required:
  261       - reg
  262       - compatible
  263       - phy-handle
  264 
  265 required:
  266   - compatible
  267   - reg
  268   - interrupts
  269   - clocks
  270   - clock-names
  271   - mediatek,ethsys
  272 
  273 unevaluatedProperties: false
  274 
  275 examples:
  276   - |
  277     #include <dt-bindings/interrupt-controller/arm-gic.h>
  278     #include <dt-bindings/interrupt-controller/irq.h>
  279     #include <dt-bindings/clock/mt7622-clk.h>
  280     #include <dt-bindings/power/mt7622-power.h>
  281 
  282     soc {
  283       #address-cells = <2>;
  284       #size-cells = <2>;
  285 
  286       ethernet: ethernet@1b100000 {
  287         compatible = "mediatek,mt7622-eth";
  288         reg = <0 0x1b100000 0 0x20000>;
  289         interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
  290                      <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
  291                      <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
  292         clocks = <&topckgen CLK_TOP_ETH_SEL>,
  293                  <&ethsys CLK_ETH_ESW_EN>,
  294                  <&ethsys CLK_ETH_GP0_EN>,
  295                  <&ethsys CLK_ETH_GP1_EN>,
  296                  <&ethsys CLK_ETH_GP2_EN>,
  297                  <&sgmiisys CLK_SGMII_TX250M_EN>,
  298                  <&sgmiisys CLK_SGMII_RX250M_EN>,
  299                  <&sgmiisys CLK_SGMII_CDR_REF>,
  300                  <&sgmiisys CLK_SGMII_CDR_FB>,
  301                  <&topckgen CLK_TOP_SGMIIPLL>,
  302                  <&apmixedsys CLK_APMIXED_ETH2PLL>;
  303         clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
  304                       "sgmii_tx250m", "sgmii_rx250m",
  305                       "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
  306                       "eth2pll";
  307         power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
  308         mediatek,ethsys = <&ethsys>;
  309         mediatek,sgmiisys = <&sgmiisys>;
  310         cci-control-port = <&cci_control2>;
  311         mediatek,pcie-mirror = <&pcie_mirror>;
  312         mediatek,hifsys = <&hifsys>;
  313         dma-coherent;
  314 
  315         #address-cells = <1>;
  316         #size-cells = <0>;
  317 
  318         mdio0: mdio-bus {
  319           #address-cells = <1>;
  320           #size-cells = <0>;
  321 
  322           phy0: ethernet-phy@0 {
  323             reg = <0>;
  324           };
  325 
  326           phy1: ethernet-phy@1 {
  327             reg = <1>;
  328           };
  329         };
  330 
  331         gmac0: mac@0 {
  332           compatible = "mediatek,eth-mac";
  333           phy-mode = "rgmii";
  334           phy-handle = <&phy0>;
  335           reg = <0>;
  336         };
  337 
  338         gmac1: mac@1 {
  339           compatible = "mediatek,eth-mac";
  340           phy-mode = "rgmii";
  341           phy-handle = <&phy1>;
  342           reg = <1>;
  343         };
  344       };
  345     };
  346 
  347   - |
  348     #include <dt-bindings/interrupt-controller/arm-gic.h>
  349     #include <dt-bindings/interrupt-controller/irq.h>
  350     #include <dt-bindings/clock/mt7622-clk.h>
  351 
  352     soc {
  353       #address-cells = <2>;
  354       #size-cells = <2>;
  355 
  356       eth: ethernet@15100000 {
  357         #define CLK_ETH_FE_EN               0
  358         #define CLK_ETH_WOCPU1_EN           3
  359         #define CLK_ETH_WOCPU0_EN           4
  360         #define CLK_TOP_NETSYS_SEL          43
  361         #define CLK_TOP_NETSYS_500M_SEL     44
  362         #define CLK_TOP_NETSYS_2X_SEL       46
  363         #define CLK_TOP_SGM_325M_SEL        47
  364         #define CLK_APMIXED_NET2PLL         1
  365         #define CLK_APMIXED_SGMPLL          3
  366 
  367         compatible = "mediatek,mt7986-eth";
  368         reg = <0 0x15100000 0 0x80000>;
  369         interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
  370                      <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
  371                      <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
  372                      <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
  373         clocks = <&ethsys CLK_ETH_FE_EN>,
  374                  <&ethsys CLK_ETH_GP2_EN>,
  375                  <&ethsys CLK_ETH_GP1_EN>,
  376                  <&ethsys CLK_ETH_WOCPU1_EN>,
  377                  <&ethsys CLK_ETH_WOCPU0_EN>,
  378                  <&sgmiisys0 CLK_SGMII_TX250M_EN>,
  379                  <&sgmiisys0 CLK_SGMII_RX250M_EN>,
  380                  <&sgmiisys0 CLK_SGMII_CDR_REF>,
  381                  <&sgmiisys0 CLK_SGMII_CDR_FB>,
  382                  <&sgmiisys1 CLK_SGMII_TX250M_EN>,
  383                  <&sgmiisys1 CLK_SGMII_RX250M_EN>,
  384                  <&sgmiisys1 CLK_SGMII_CDR_REF>,
  385                  <&sgmiisys1 CLK_SGMII_CDR_FB>,
  386                  <&topckgen CLK_TOP_NETSYS_SEL>,
  387                  <&topckgen CLK_TOP_NETSYS_SEL>;
  388         clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
  389                       "sgmii_tx250m", "sgmii_rx250m",
  390                       "sgmii_cdr_ref", "sgmii_cdr_fb",
  391                       "sgmii2_tx250m", "sgmii2_rx250m",
  392                       "sgmii2_cdr_ref", "sgmii2_cdr_fb",
  393                       "netsys0", "netsys1";
  394         mediatek,ethsys = <&ethsys>;
  395         mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
  396         assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
  397                           <&topckgen CLK_TOP_SGM_325M_SEL>;
  398         assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
  399                                  <&apmixedsys CLK_APMIXED_SGMPLL>;
  400 
  401         #address-cells = <1>;
  402         #size-cells = <0>;
  403 
  404         mdio: mdio-bus {
  405           #address-cells = <1>;
  406           #size-cells = <0>;
  407 
  408           phy5: ethernet-phy@0 {
  409             compatible = "ethernet-phy-id67c9.de0a";
  410             phy-mode = "2500base-x";
  411             reset-gpios = <&pio 6 1>;
  412             reset-deassert-us = <20000>;
  413             reg = <5>;
  414           };
  415 
  416           phy6: ethernet-phy@1 {
  417             compatible = "ethernet-phy-id67c9.de0a";
  418             phy-mode = "2500base-x";
  419             reg = <6>;
  420           };
  421         };
  422 
  423         mac0: mac@0 {
  424           compatible = "mediatek,eth-mac";
  425           phy-mode = "2500base-x";
  426           phy-handle = <&phy5>;
  427           reg = <0>;
  428         };
  429 
  430         mac1: mac@1 {
  431           compatible = "mediatek,eth-mac";
  432           phy-mode = "2500base-x";
  433           phy-handle = <&phy6>;
  434           reg = <1>;
  435         };
  436       };
  437     };
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