mediatek-dwmac.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: MediaTek DWMAC glue layer controller
    8 
    9 maintainers:
   10   - Biao Huang <biao.huang@mediatek.com>
   11 
   12 description:
   13   This file documents platform glue layer for stmmac.
   14 
   15 # We need a select here so we don't match all nodes with 'snps,dwmac'
   16 select:
   17   properties:
   18     compatible:
   19       contains:
   20         enum:
   21           - mediatek,mt2712-gmac
   22           - mediatek,mt8195-gmac
   23   required:
   24     - compatible
   25 
   26 allOf:
   27   - $ref: "snps,dwmac.yaml#"
   28 
   29 properties:
   30   compatible:
   31     oneOf:
   32       - items:
   33           - enum:
   34               - mediatek,mt2712-gmac
   35           - const: snps,dwmac-4.20a
   36       - items:
   37           - enum:
   38               - mediatek,mt8195-gmac
   39           - const: snps,dwmac-5.10a
   40 
   41   clocks:
   42     minItems: 5
   43     items:
   44       - description: AXI clock
   45       - description: APB clock
   46       - description: MAC Main clock
   47       - description: PTP clock
   48       - description: RMII reference clock provided by MAC
   49       - description: MAC clock gate
   50 
   51   clock-names:
   52     minItems: 5
   53     items:
   54       - const: axi
   55       - const: apb
   56       - const: mac_main
   57       - const: ptp_ref
   58       - const: rmii_internal
   59       - const: mac_cg
   60 
   61   power-domains:
   62     maxItems: 1
   63 
   64   mediatek,pericfg:
   65     $ref: /schemas/types.yaml#/definitions/phandle
   66     description:
   67       The phandle to the syscon node that control ethernet
   68       interface and timing delay.
   69 
   70   mediatek,tx-delay-ps:
   71     description:
   72       The internal TX clock delay (provided by this driver) in nanoseconds.
   73       For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
   74       or will round down. Range 0~31*170.
   75       For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,
   76       or will round down. Range 0~31*550.
   77       For MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple of 290,
   78       or will round down. Range 0~31*290.
   79 
   80   mediatek,rx-delay-ps:
   81     description:
   82       The internal RX clock delay (provided by this driver) in nanoseconds.
   83       For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
   84       or will round down. Range 0~31*170.
   85       For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,
   86       or will round down. Range 0~31*550.
   87       For MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple
   88       of 290, or will round down. Range 0~31*290.
   89 
   90   mediatek,rmii-rxc:
   91     type: boolean
   92     description:
   93       If present, indicates that the RMII reference clock, which is from external
   94       PHYs, is connected to RXC pin. Otherwise, is connected to TXC pin.
   95 
   96   mediatek,rmii-clk-from-mac:
   97     type: boolean
   98     description:
   99       If present, indicates that MAC provides the RMII reference clock, which
  100       outputs to TXC pin only.
  101 
  102   mediatek,txc-inverse:
  103     type: boolean
  104     description:
  105       If present, indicates that
  106       1. tx clock will be inversed in MII/RGMII case,
  107       2. tx clock inside MAC will be inversed relative to reference clock
  108          which is from external PHYs in RMII case, and it rarely happen.
  109       3. the reference clock, which outputs to TXC pin will be inversed in RMII case
  110          when the reference clock is from MAC.
  111 
  112   mediatek,rxc-inverse:
  113     type: boolean
  114     description:
  115       If present, indicates that
  116       1. rx clock will be inversed in MII/RGMII case.
  117       2. reference clock will be inversed when arrived at MAC in RMII case, when
  118          the reference clock is from external PHYs.
  119       3. the inside clock, which be sent to MAC, will be inversed in RMII case when
  120          the reference clock is from MAC.
  121 
  122   mediatek,mac-wol:
  123     type: boolean
  124     description:
  125       If present, indicates that MAC supports WOL(Wake-On-LAN), and MAC WOL will be enabled.
  126       Otherwise, PHY WOL is perferred.
  127 
  128 required:
  129   - compatible
  130   - reg
  131   - interrupts
  132   - interrupt-names
  133   - clocks
  134   - clock-names
  135   - phy-mode
  136   - mediatek,pericfg
  137 
  138 unevaluatedProperties: false
  139 
  140 examples:
  141   - |
  142     #include <dt-bindings/clock/mt2712-clk.h>
  143     #include <dt-bindings/gpio/gpio.h>
  144     #include <dt-bindings/interrupt-controller/arm-gic.h>
  145     #include <dt-bindings/interrupt-controller/irq.h>
  146     #include <dt-bindings/power/mt2712-power.h>
  147 
  148     eth: ethernet@1101c000 {
  149         compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a";
  150         reg = <0x1101c000 0x1300>;
  151         interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
  152         interrupt-names = "macirq";
  153         phy-mode ="rgmii-rxid";
  154         mac-address = [00 55 7b b5 7d f7];
  155         clock-names = "axi",
  156                       "apb",
  157                       "mac_main",
  158                       "ptp_ref",
  159                       "rmii_internal";
  160         clocks = <&pericfg CLK_PERI_GMAC>,
  161                  <&pericfg CLK_PERI_GMAC_PCLK>,
  162                  <&topckgen CLK_TOP_ETHER_125M_SEL>,
  163                  <&topckgen CLK_TOP_ETHER_50M_SEL>,
  164                  <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
  165         assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
  166                           <&topckgen CLK_TOP_ETHER_50M_SEL>,
  167                           <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
  168         assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
  169                                  <&topckgen CLK_TOP_APLL1_D3>,
  170                                  <&topckgen CLK_TOP_ETHERPLL_50M>;
  171         power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
  172         mediatek,pericfg = <&pericfg>;
  173         mediatek,tx-delay-ps = <1530>;
  174         snps,txpbl = <1>;
  175         snps,rxpbl = <1>;
  176         snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
  177         snps,reset-delays-us = <0 10000 10000>;
  178     };

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