qca,ar71xx.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/net/qca,ar71xx.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: QCA AR71XX MAC
    8 
    9 allOf:
   10   - $ref: ethernet-controller.yaml#
   11 
   12 maintainers:
   13   - Oleksij Rempel <o.rempel@pengutronix.de>
   14 
   15 properties:
   16   compatible:
   17     oneOf:
   18       - items:
   19           - enum:
   20               - qca,ar7100-eth   # Atheros AR7100
   21               - qca,ar7240-eth   # Atheros AR7240
   22               - qca,ar7241-eth   # Atheros AR7241
   23               - qca,ar7242-eth   # Atheros AR7242
   24               - qca,ar9130-eth   # Atheros AR9130
   25               - qca,ar9330-eth   # Atheros AR9330
   26               - qca,ar9340-eth   # Atheros AR9340
   27               - qca,qca9530-eth  # Qualcomm Atheros QCA9530
   28               - qca,qca9550-eth  # Qualcomm Atheros QCA9550
   29               - qca,qca9560-eth  # Qualcomm Atheros QCA9560
   30 
   31   reg:
   32     maxItems: 1
   33 
   34   interrupts:
   35     maxItems: 1
   36 
   37   clocks:
   38     items:
   39       - description: MAC main clock
   40       - description: MDIO clock
   41 
   42   clock-names:
   43     items:
   44       - const: eth
   45       - const: mdio
   46 
   47   resets:
   48     items:
   49       - description: MAC reset
   50       - description: MDIO reset
   51 
   52   reset-names:
   53     items:
   54       - const: mac
   55       - const: mdio
   56 
   57   mdio:
   58     $ref: mdio.yaml#
   59     unevaluatedProperties: false
   60 
   61 required:
   62   - compatible
   63   - reg
   64   - interrupts
   65   - phy-mode
   66   - clocks
   67   - clock-names
   68   - resets
   69   - reset-names
   70 
   71 unevaluatedProperties: false
   72 
   73 examples:
   74   # Lager board
   75   - |
   76     eth0: ethernet@19000000 {
   77         compatible = "qca,ar9330-eth";
   78         reg = <0x19000000 0x200>;
   79         interrupts = <4>;
   80         resets = <&rst 9>, <&rst 22>;
   81         reset-names = "mac", "mdio";
   82         clocks = <&pll 1>, <&pll 2>;
   83         clock-names = "eth", "mdio";
   84         phy-mode = "mii";
   85         phy-handle = <&phy_port4>;
   86     };
   87 
   88     eth1: ethernet@1a000000 {
   89         compatible = "qca,ar9330-eth";
   90         reg = <0x1a000000 0x200>;
   91         interrupts = <5>;
   92         resets = <&rst 13>, <&rst 23>;
   93         reset-names = "mac", "mdio";
   94         clocks = <&pll 1>, <&pll 2>;
   95         clock-names = "eth", "mdio";
   96 
   97         phy-mode = "gmii";
   98 
   99         fixed-link {
  100             speed = <1000>;
  101             full-duplex;
  102         };
  103 
  104         mdio {
  105             #address-cells = <1>;
  106             #size-cells = <0>;
  107 
  108             switch10: switch@10 {
  109                 compatible = "qca,ar9331-switch";
  110                 reg = <0x10>;
  111                 resets = <&rst 8>;
  112                 reset-names = "switch";
  113 
  114                 interrupt-parent = <&miscintc>;
  115                 interrupts = <12>;
  116 
  117                 interrupt-controller;
  118                 #interrupt-cells = <1>;
  119 
  120                 ports {
  121                     #address-cells = <1>;
  122                     #size-cells = <0>;
  123 
  124                     switch_port0: port@0 {
  125                         reg = <0x0>;
  126                         label = "cpu";
  127                         ethernet = <&eth1>;
  128 
  129                         phy-mode = "gmii";
  130 
  131                         fixed-link {
  132                             speed = <1000>;
  133                             full-duplex;
  134                         };
  135                     };
  136 
  137                     switch_port1: port@1 {
  138                         reg = <0x1>;
  139                         phy-handle = <&phy_port0>;
  140                         phy-mode = "internal";
  141                     };
  142 
  143                     switch_port2: port@2 {
  144                         reg = <0x2>;
  145                         phy-handle = <&phy_port1>;
  146                         phy-mode = "internal";
  147                     };
  148 
  149                     switch_port3: port@3 {
  150                         reg = <0x3>;
  151                         phy-handle = <&phy_port2>;
  152                         phy-mode = "internal";
  153                     };
  154 
  155                     switch_port4: port@4 {
  156                         reg = <0x4>;
  157                         phy-handle = <&phy_port3>;
  158                         phy-mode = "internal";
  159                     };
  160                 };
  161 
  162                 mdio {
  163                     #address-cells = <1>;
  164                     #size-cells = <0>;
  165 
  166                     interrupt-parent = <&switch10>;
  167 
  168                     phy_port0: ethernet-phy@0 {
  169                         reg = <0x0>;
  170                         interrupts = <0>;
  171                     };
  172 
  173                     phy_port1: ethernet-phy@1 {
  174                         reg = <0x1>;
  175                         interrupts = <0>;
  176                     };
  177 
  178                     phy_port2: ethernet-phy@2 {
  179                         reg = <0x2>;
  180                         interrupts = <0>;
  181                     };
  182 
  183                     phy_port3: ethernet-phy@3 {
  184                         reg = <0x3>;
  185                         interrupts = <0>;
  186                     };
  187 
  188                     phy_port4: ethernet-phy@4 {
  189                         reg = <0x4>;
  190                         interrupts = <0>;
  191                     };
  192                 };
  193             };
  194         };
  195     };

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