1 OpenRISC Generic SoC
2 ====================
3
4 Boards and FPGA SoC's which support the OpenRISC standard platform. The
5 platform essentially follows the conventions of the OpenRISC architecture
6 specification, however some aspects, such as the boot protocol have been defined
7 by the Linux port.
8
9 Required properties
10 -------------------
11 - compatible: Must include "opencores,or1ksim"
12
13 CPU nodes:
14 ----------
15 A "cpus" node is required. Required properties:
16 - #address-cells: Must be 1.
17 - #size-cells: Must be 0.
18 A CPU sub-node is also required for at least CPU 0. Since the topology may
19 be probed via CPS, it is not necessary to specify secondary CPUs. Required
20 properties:
21 - compatible: Must be "opencores,or1200-rtlsvn481".
22 - reg: CPU number.
23 - clock-frequency: The CPU clock frequency in Hz.
24 Example:
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28 cpu@0 {
29 compatible = "opencores,or1200-rtlsvn481";
30 reg = <0>;
31 clock-frequency = <20000000>;
32 };
33 };
34
35
36 Boot protocol
37 -------------
38 The bootloader may pass the following arguments to the kernel:
39 - r3: address of a flattened device-tree blob or 0x0.
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