brcm,iproc-pcie.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Broadcom iProc PCIe controller with the platform bus interface
    8 
    9 maintainers:
   10   - Ray Jui <ray.jui@broadcom.com>
   11   - Scott Branden <scott.branden@broadcom.com>
   12 
   13 allOf:
   14   - $ref: /schemas/pci/pci-bus.yaml#
   15   - $ref: /schemas/interrupt-controller/msi-controller.yaml#
   16 
   17 properties:
   18   compatible:
   19     items:
   20       - enum:
   21           # for the first generation of PAXB based controller, used in SoCs
   22           # including NSP, Cygnus, NS2, and Pegasus
   23           - brcm,iproc-pcie
   24           # for the second generation of PAXB-based controllers, used in
   25           # Stingray
   26           - brcm,iproc-pcie-paxb-v2
   27           # For the first generation of PAXC based controller, used in NS2
   28           - brcm,iproc-pcie-paxc
   29           # For the second generation of PAXC based controller, used in Stingray
   30           - brcm,iproc-pcie-paxc-v2
   31 
   32   reg:
   33     maxItems: 1
   34     description: >
   35        Base address and length of the PCIe controller I/O register space
   36 
   37   interrupt-map: true
   38 
   39   interrupt-map-mask: true
   40 
   41   "#interrupt-cells":
   42     const: 1
   43 
   44   ranges:
   45     minItems: 1
   46     maxItems: 2
   47     description: >
   48       Ranges for the PCI memory and I/O regions
   49 
   50   phys:
   51     maxItems: 1
   52 
   53   phy-names:
   54     items:
   55       - const: pcie-phy
   56 
   57   bus-range: true
   58 
   59   dma-coherent: true
   60 
   61   "#address-cells": true
   62 
   63   "#size-cells": true
   64 
   65   device_type: true
   66 
   67   brcm,pcie-ob:
   68     type: boolean
   69     description: >
   70       Some iProc SoCs do not have the outbound address mapping done by the
   71       ASIC after power on reset. In this case, SW needs to configure it
   72 
   73   brcm,pcie-ob-axi-offset:
   74     $ref: /schemas/types.yaml#/definitions/uint32
   75     description: >
   76        The offset from the AXI address to the internal address used by the
   77        iProc PCIe core (not the PCIe address)
   78 
   79   msi:
   80     type: object
   81     properties:
   82       compatible:
   83         items:
   84           - const: brcm,iproc-msi
   85 
   86   msi-parent: true
   87 
   88   msi-controller: true
   89 
   90   brcm,pcie-msi-inten:
   91     type: boolean
   92     description: >
   93       Needs to be present for some older iProc platforms that require the
   94       interrupt enable registers to be set explicitly to enable MSI
   95 
   96 dependencies:
   97   brcm,pcie-ob-axi-offset: ["brcm,pcie-ob"]
   98   brcm,pcie-msi-inten: [msi-controller]
   99 
  100 required:
  101   - compatible
  102   - reg
  103   - ranges
  104 
  105 if:
  106   properties:
  107     compatible:
  108       contains:
  109         enum:
  110           - brcm,iproc-pcie
  111 then:
  112   required:
  113     - interrupt-map
  114     - interrupt-map-mask
  115 
  116 unevaluatedProperties: false
  117 
  118 examples:
  119   - |
  120    #include <dt-bindings/interrupt-controller/arm-gic.h>
  121 
  122    bus {
  123       #address-cells = <1>;
  124       #size-cells = <1>;
  125            pcie0: pcie@18012000 {
  126               compatible = "brcm,iproc-pcie";
  127               reg = <0x18012000 0x1000>;
  128 
  129               #interrupt-cells = <1>;
  130               interrupt-map-mask = <0 0 0 0>;
  131               interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
  132 
  133               linux,pci-domain = <0>;
  134 
  135               bus-range = <0x00 0xff>;
  136 
  137               #address-cells = <3>;
  138               #size-cells = <2>;
  139               device_type = "pci";
  140               ranges = <0x81000000 0 0     0x28000000 0 0x00010000>,
  141                    <0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
  142 
  143               phys = <&phy 0 5>;
  144               phy-names = "pcie-phy";
  145 
  146               brcm,pcie-ob;
  147               brcm,pcie-ob-axi-offset = <0x00000000>;
  148 
  149               msi-parent = <&msi0>;
  150 
  151               /* iProc event queue based MSI */
  152               msi0: msi {
  153                  compatible = "brcm,iproc-msi";
  154                  msi-controller;
  155                  interrupt-parent = <&gic>;
  156                  interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
  157                          <GIC_SPI 97 IRQ_TYPE_NONE>,
  158                          <GIC_SPI 98 IRQ_TYPE_NONE>,
  159                          <GIC_SPI 99 IRQ_TYPE_NONE>;
  160               };
  161            };
  162 
  163            pcie1: pcie@18013000 {
  164               compatible = "brcm,iproc-pcie";
  165               reg = <0x18013000 0x1000>;
  166 
  167               #interrupt-cells = <1>;
  168               interrupt-map-mask = <0 0 0 0>;
  169               interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
  170 
  171               linux,pci-domain = <1>;
  172 
  173               bus-range = <0x00 0xff>;
  174 
  175               #address-cells = <3>;
  176               #size-cells = <2>;
  177               device_type = "pci";
  178               ranges = <0x81000000 0 0     0x48000000 0 0x00010000>,
  179                    <0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
  180 
  181               phys = <&phy 1 6>;
  182               phy-names = "pcie-phy";
  183            };
  184     };

Cache object: 254414fcc7bfc18c802baad51d8f9f37

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/pci/brcm,iproc-pcie.yaml

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sys/contrib/device-tree/Bindings/pci/brcm,iproc-pcie.yaml