pci-keystone.txt

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    1 TI Keystone PCIe interface
    2 
    3 Keystone PCI host Controller is based on the Synopsys DesignWare PCI
    4 hardware version 3.65.  It shares common functions with the PCIe DesignWare
    5 core driver and inherits common properties defined in
    6 Documentation/devicetree/bindings/pci/designware-pcie.txt
    7 
    8 Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
    9 for the details of DesignWare DT bindings.  Additional properties are
   10 described here as well as properties that are not applicable.
   11 
   12 Required Properties:-
   13 
   14 compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
   15                Should be "ti,am654-pcie-rc" for RC on AM654x SoC
   16 reg: Three register ranges as listed in the reg-names property
   17 reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
   18            TI specific application registers, "config" for the
   19            configuration space address
   20 
   21 pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
   22         interrupt-cells: should be set to 1
   23         interrupts: GIC interrupt lines connected to PCI MSI interrupt lines
   24         (required if the compatible is "ti,keystone-pcie")
   25 msi-map: As specified in Documentation/devicetree/bindings/pci/pci-msi.txt
   26          (required if the compatible is "ti,am654-pcie-rc".
   27 
   28 ti,syscon-pcie-id : phandle to the device control module required to set device
   29                     id and vendor id.
   30 ti,syscon-pcie-mode : phandle to the device control module required to configure
   31                       PCI in either RC mode or EP mode.
   32 
   33  Example:
   34         pcie_msi_intc: msi-interrupt-controller {
   35                         interrupt-controller;
   36                         #interrupt-cells = <1>;
   37                         interrupt-parent = <&gic>;
   38                         interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
   39                                         <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
   40                                         <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
   41                                         <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
   42                                         <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
   43                                         <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
   44                                         <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
   45                                         <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
   46         };
   47 
   48 pcie_intc: Interrupt controller device node for Legacy IRQ chip
   49         interrupt-cells: should be set to 1
   50 
   51  Example:
   52         pcie_intc: legacy-interrupt-controller {
   53                 interrupt-controller;
   54                 #interrupt-cells = <1>;
   55                 interrupt-parent = <&gic>;
   56                 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
   57                         <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
   58                         <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
   59                         <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
   60         };
   61 
   62 Optional properties:-
   63         phys: phandle to generic Keystone SerDes PHY for PCI
   64         phy-names: name of the generic Keystone SerDes PHY for PCI
   65           - If boot loader already does PCI link establishment, then phys and
   66             phy-names shouldn't be present.
   67         interrupts: platform interrupt for error interrupts.
   68 
   69 DesignWare DT Properties not applicable for Keystone PCI
   70 
   71 1. pcie_bus clock-names not used.  Instead, a phandle to phys is used.
   72 
   73 AM654 PCIe Endpoint
   74 ===================
   75 
   76 Required Properties:-
   77 
   78 compatibility: Should be "ti,am654-pcie-ep" for EP on AM654x SoC
   79 reg: Four register ranges as listed in the reg-names property
   80 reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
   81            TI specific application registers, "atu" for the
   82            Address Translation Unit configuration registers and
   83            "addr_space" used to map remote RC address space
   84 num-ib-windows: As specified in
   85                 Documentation/devicetree/bindings/pci/designware-pcie.txt
   86 num-ob-windows: As specified in
   87                 Documentation/devicetree/bindings/pci/designware-pcie.txt
   88 num-lanes: As specified in
   89            Documentation/devicetree/bindings/pci/designware-pcie.txt
   90 power-domains: As documented by the generic PM domain bindings in
   91                Documentation/devicetree/bindings/power/power_domain.txt.
   92 ti,syscon-pcie-mode: phandle to the device control module required to configure
   93                       PCI in either RC mode or EP mode.
   94 
   95 Optional properties:-
   96 
   97 phys: list of PHY specifiers (used by generic PHY framework)
   98 phy-names: must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
   99                number of lanes as specified in *num-lanes* property.
  100 ("phys" and "phy-names" DT bindings are specified in
  101 Documentation/devicetree/bindings/phy/phy-bindings.txt)
  102 interrupts: platform interrupt for error interrupts.
  103 
  104 pcie-ep {
  105         compatible = "ti,am654-pcie-ep";
  106         reg =  <0x5500000 0x1000>, <0x5501000 0x1000>,
  107                <0x10000000 0x8000000>, <0x5506000 0x1000>;
  108         reg-names = "app", "dbics", "addr_space", "atu";
  109         power-domains = <&k3_pds 120>;
  110         ti,syscon-pcie-mode = <&pcie0_mode>;
  111         num-lanes = <1>;
  112         num-ib-windows = <16>;
  113         num-ob-windows = <16>;
  114         interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
  115 };

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