rockchip-dw-pcie.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: DesignWare based PCIe controller on Rockchip SoCs
    8 
    9 maintainers:
   10   - Shawn Lin <shawn.lin@rock-chips.com>
   11   - Simon Xue <xxm@rock-chips.com>
   12   - Heiko Stuebner <heiko@sntech.de>
   13 
   14 description: |+
   15   RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
   16   PCIe IP and thus inherits all the common properties defined in
   17   designware-pcie.txt.
   18 
   19 allOf:
   20   - $ref: /schemas/pci/pci-bus.yaml#
   21 
   22 properties:
   23   compatible:
   24     items:
   25       - const: rockchip,rk3568-pcie
   26 
   27   reg:
   28     items:
   29       - description: Data Bus Interface (DBI) registers
   30       - description: Rockchip designed configuration registers
   31       - description: Config registers
   32 
   33   reg-names:
   34     items:
   35       - const: dbi
   36       - const: apb
   37       - const: config
   38 
   39   clocks:
   40     items:
   41       - description: AHB clock for PCIe master
   42       - description: AHB clock for PCIe slave
   43       - description: AHB clock for PCIe dbi
   44       - description: APB clock for PCIe
   45       - description: Auxiliary clock for PCIe
   46 
   47   clock-names:
   48     items:
   49       - const: aclk_mst
   50       - const: aclk_slv
   51       - const: aclk_dbi
   52       - const: pclk
   53       - const: aux
   54 
   55   msi-map: true
   56 
   57   num-lanes: true
   58 
   59   phys:
   60     maxItems: 1
   61 
   62   phy-names:
   63     const: pcie-phy
   64 
   65   power-domains:
   66     maxItems: 1
   67 
   68   ranges:
   69     maxItems: 2
   70 
   71   resets:
   72     maxItems: 1
   73 
   74   reset-names:
   75     const: pipe
   76 
   77   vpcie3v3-supply: true
   78 
   79 required:
   80   - compatible
   81   - reg
   82   - reg-names
   83   - clocks
   84   - clock-names
   85   - msi-map
   86   - num-lanes
   87   - phys
   88   - phy-names
   89   - power-domains
   90   - resets
   91   - reset-names
   92 
   93 unevaluatedProperties: false
   94 
   95 examples:
   96   - |
   97 
   98     bus {
   99         #address-cells = <2>;
  100         #size-cells = <2>;
  101 
  102         pcie3x2: pcie@fe280000 {
  103             compatible = "rockchip,rk3568-pcie";
  104             reg = <0x3 0xc0800000 0x0 0x390000>,
  105                   <0x0 0xfe280000 0x0 0x10000>,
  106                   <0x3 0x80000000 0x0 0x100000>;
  107             reg-names = "dbi", "apb", "config";
  108             bus-range = <0x20 0x2f>;
  109             clocks = <&cru 143>, <&cru 144>,
  110                      <&cru 145>, <&cru 146>,
  111                      <&cru 147>;
  112             clock-names = "aclk_mst", "aclk_slv",
  113                           "aclk_dbi", "pclk",
  114                           "aux";
  115             device_type = "pci";
  116             linux,pci-domain = <2>;
  117             max-link-speed = <2>;
  118             msi-map = <0x2000 &its 0x2000 0x1000>;
  119             num-lanes = <2>;
  120             phys = <&pcie30phy>;
  121             phy-names = "pcie-phy";
  122             power-domains = <&power 15>;
  123             ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
  124                      <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
  125             resets = <&cru 193>;
  126             reset-names = "pipe";
  127             #address-cells = <3>;
  128             #size-cells = <2>;
  129         };
  130     };
  131 ...

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