The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/pci/ti,j721e-pci-host.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
    3 %YAML 1.2
    4 ---
    5 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#"
    6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
    7 
    8 title: TI J721E PCI Host (PCIe Wrapper)
    9 
   10 maintainers:
   11   - Kishon Vijay Abraham I <kishon@ti.com>
   12 
   13 allOf:
   14   - $ref: "cdns-pcie-host.yaml#"
   15 
   16 properties:
   17   compatible:
   18     oneOf:
   19       - const: ti,j721e-pcie-host
   20       - description: PCIe controller in AM64
   21         items:
   22           - const: ti,am64-pcie-host
   23           - const: ti,j721e-pcie-host
   24       - description: PCIe controller in J7200
   25         items:
   26           - const: ti,j7200-pcie-host
   27           - const: ti,j721e-pcie-host
   28 
   29   reg:
   30     maxItems: 4
   31 
   32   reg-names:
   33     items:
   34       - const: intd_cfg
   35       - const: user_cfg
   36       - const: reg
   37       - const: cfg
   38 
   39   ti,syscon-pcie-ctrl:
   40     $ref: /schemas/types.yaml#/definitions/phandle-array
   41     items:
   42       - items:
   43           - description: Phandle to the SYSCON entry
   44           - description: pcie_ctrl register offset within SYSCON
   45     description: Specifier for configuring PCIe mode and link speed.
   46 
   47   power-domains:
   48     maxItems: 1
   49 
   50   clocks:
   51     minItems: 1
   52     maxItems: 2
   53     description: |+
   54       clock-specifier to represent input to the PCIe for 1 item.
   55       2nd item if present represents reference clock to the connector.
   56 
   57   clock-names:
   58     minItems: 1
   59     items:
   60       - const: fck
   61       - const: pcie_refclk
   62 
   63   dma-coherent: true
   64 
   65   vendor-id:
   66     const: 0x104c
   67 
   68   device-id:
   69     oneOf:
   70       - items:
   71           - const: 0xb00d
   72       - items:
   73           - const: 0xb00f
   74       - items:
   75           - const: 0xb010
   76 
   77   msi-map: true
   78 
   79 required:
   80   - compatible
   81   - reg
   82   - reg-names
   83   - ti,syscon-pcie-ctrl
   84   - max-link-speed
   85   - num-lanes
   86   - power-domains
   87   - clocks
   88   - clock-names
   89   - vendor-id
   90   - device-id
   91   - msi-map
   92   - dma-ranges
   93   - ranges
   94   - reset-gpios
   95   - phys
   96   - phy-names
   97 
   98 unevaluatedProperties: false
   99 
  100 examples:
  101   - |
  102     #include <dt-bindings/soc/ti,sci_pm_domain.h>
  103     #include <dt-bindings/gpio/gpio.h>
  104 
  105     bus {
  106         #address-cells = <2>;
  107         #size-cells = <2>;
  108 
  109         pcie0_rc: pcie@2900000 {
  110             compatible = "ti,j721e-pcie-host";
  111             reg = <0x00 0x02900000 0x00 0x1000>,
  112                   <0x00 0x02907000 0x00 0x400>,
  113                   <0x00 0x0d000000 0x00 0x00800000>,
  114                   <0x00 0x10000000 0x00 0x00001000>;
  115             reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
  116             ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
  117             max-link-speed = <3>;
  118             num-lanes = <2>;
  119             power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
  120             clocks = <&k3_clks 239 1>;
  121             clock-names = "fck";
  122             device_type = "pci";
  123             #address-cells = <3>;
  124             #size-cells = <2>;
  125             bus-range = <0x0 0xf>;
  126             vendor-id = <0x104c>;
  127             device-id = <0xb00d>;
  128             msi-map = <0x0 &gic_its 0x0 0x10000>;
  129             dma-coherent;
  130             reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
  131             phys = <&serdes0_pcie_link>;
  132             phy-names = "pcie-phy";
  133             ranges = <0x01000000 0x0 0x10001000  0x00 0x10001000  0x0 0x0010000>,
  134                      <0x02000000 0x0 0x10011000  0x00 0x10011000  0x0 0x7fef000>;
  135             dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
  136         };
  137     };

Cache object: 6f0c4952b3b697db59076e2707cc2b4f


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