mediatek,hdmi-phy.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 # Copyright (c) 2020 MediaTek
    3 %YAML 1.2
    4 ---
    5 $id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
    6 $schema: http://devicetree.org/meta-schemas/core.yaml#
    7 
    8 title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding
    9 
   10 maintainers:
   11   - Chun-Kuang Hu <chunkuang.hu@kernel.org>
   12   - Philipp Zabel <p.zabel@pengutronix.de>
   13   - Chunfeng Yun <chunfeng.yun@mediatek.com>
   14 
   15 description: |
   16   The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
   17   output and drives the HDMI pads.
   18 
   19 properties:
   20   $nodename:
   21     pattern: "^hdmi-phy@[0-9a-f]+$"
   22 
   23   compatible:
   24     oneOf:
   25       - items:
   26           - enum:
   27               - mediatek,mt7623-hdmi-phy
   28           - const: mediatek,mt2701-hdmi-phy
   29       - const: mediatek,mt2701-hdmi-phy
   30       - const: mediatek,mt8173-hdmi-phy
   31 
   32   reg:
   33     maxItems: 1
   34 
   35   clocks:
   36     items:
   37       - description: PLL reference clock
   38 
   39   clock-names:
   40     items:
   41       - const: pll_ref
   42 
   43   clock-output-names:
   44     items:
   45       - const: hdmitx_dig_cts
   46 
   47   "#phy-cells":
   48     const: 0
   49 
   50   "#clock-cells":
   51     const: 0
   52 
   53   mediatek,ibias:
   54     description:
   55       TX DRV bias current for < 1.65Gbps
   56     $ref: /schemas/types.yaml#/definitions/uint32
   57     minimum: 0
   58     maximum: 63
   59     default: 0xa
   60 
   61   mediatek,ibias_up:
   62     description:
   63       TX DRV bias current for >= 1.65Gbps
   64     $ref: /schemas/types.yaml#/definitions/uint32
   65     minimum: 0
   66     maximum: 63
   67     default: 0x1c
   68 
   69 required:
   70   - compatible
   71   - reg
   72   - clocks
   73   - clock-names
   74   - clock-output-names
   75   - "#phy-cells"
   76   - "#clock-cells"
   77 
   78 additionalProperties: false
   79 
   80 examples:
   81   - |
   82     #include <dt-bindings/clock/mt8173-clk.h>
   83     hdmi_phy: hdmi-phy@10209100 {
   84         compatible = "mediatek,mt8173-hdmi-phy";
   85         reg = <0x10209100 0x24>;
   86         clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
   87         clock-names = "pll_ref";
   88         clock-output-names = "hdmitx_dig_cts";
   89         mediatek,ibias = <0xa>;
   90         mediatek,ibias_up = <0x1c>;
   91         #clock-cells = <0>;
   92         #phy-cells = <0>;
   93     };
   94 
   95 ...

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/phy/mediatek,hdmi-phy.yaml

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sys/contrib/device-tree/Bindings/phy/mediatek,hdmi-phy.yaml