mediatek,xsphy.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 # Copyright (c) 2020 MediaTek
    3 %YAML 1.2
    4 ---
    5 $id: http://devicetree.org/schemas/phy/mediatek,xsphy.yaml#
    6 $schema: http://devicetree.org/meta-schemas/core.yaml#
    7 
    8 title: MediaTek XS-PHY Controller Device Tree Bindings
    9 
   10 maintainers:
   11   - Chunfeng Yun <chunfeng.yun@mediatek.com>
   12 
   13 description: |
   14   The XS-PHY controller supports physical layer functionality for USB3.1
   15   GEN2 controller on MediaTek SoCs.
   16 
   17   Banks layout of xsphy
   18   ----------------------------------
   19   port        offset    bank
   20   u2 port0    0x0000    MISC
   21               0x0100    FMREG
   22               0x0300    U2PHY_COM
   23   u2 port1    0x1000    MISC
   24               0x1100    FMREG
   25               0x1300    U2PHY_COM
   26   u2 port2    0x2000    MISC
   27               ...
   28   u31 common  0x3000    DIG_GLB
   29               0x3100    PHYA_GLB
   30   u31 port0   0x3400    DIG_LN_TOP
   31               0x3500    DIG_LN_TX0
   32               0x3600    DIG_LN_RX0
   33               0x3700    DIG_LN_DAIF
   34               0x3800    PHYA_LN
   35   u31 port1   0x3a00    DIG_LN_TOP
   36               0x3b00    DIG_LN_TX0
   37               0x3c00    DIG_LN_RX0
   38               0x3d00    DIG_LN_DAIF
   39               0x3e00    PHYA_LN
   40               ...
   41   DIG_GLB & PHYA_GLB are shared by U31 ports.
   42 
   43 properties:
   44   $nodename:
   45     pattern: "^xs-phy@[0-9a-f]+$"
   46 
   47   compatible:
   48     items:
   49       - enum:
   50           - mediatek,mt3611-xsphy
   51           - mediatek,mt3612-xsphy
   52       - const: mediatek,xsphy
   53 
   54   reg:
   55     description:
   56       Register shared by multiple U3 ports, exclude port's private register,
   57       if only U2 ports provided, shouldn't use the property.
   58     maxItems: 1
   59 
   60   "#address-cells":
   61     enum: [1, 2]
   62 
   63   "#size-cells":
   64     enum: [1, 2]
   65 
   66   ranges: true
   67 
   68   mediatek,src-ref-clk-mhz:
   69     description:
   70       Frequency of reference clock for slew rate calibrate
   71     default: 26
   72 
   73   mediatek,src-coef:
   74     description:
   75       Coefficient for slew rate calibrate, depends on SoC process
   76     $ref: /schemas/types.yaml#/definitions/uint32
   77     default: 17
   78 
   79 # Required child node:
   80 patternProperties:
   81   "^usb-phy@[0-9a-f]+$":
   82     type: object
   83     description:
   84       A sub-node is required for each port the controller provides.
   85       Address range information including the usual 'reg' property
   86       is used inside these nodes to describe the controller's topology.
   87 
   88     properties:
   89       reg:
   90         maxItems: 1
   91 
   92       clocks:
   93         items:
   94           - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
   95 
   96       clock-names:
   97         items:
   98           - const: ref
   99 
  100       "#phy-cells":
  101         const: 1
  102         description: |
  103           The cells contain the following arguments.
  104 
  105           - description: The PHY type
  106               enum:
  107                 - PHY_TYPE_USB2
  108                 - PHY_TYPE_USB3
  109 
  110       # The following optional vendor properties are only for debug or HQA test
  111       mediatek,eye-src:
  112         description:
  113           The value of slew rate calibrate (U2 phy)
  114         $ref: /schemas/types.yaml#/definitions/uint32
  115         minimum: 1
  116         maximum: 7
  117 
  118       mediatek,eye-vrt:
  119         description:
  120           The selection of VRT reference voltage (U2 phy)
  121         $ref: /schemas/types.yaml#/definitions/uint32
  122         minimum: 1
  123         maximum: 7
  124 
  125       mediatek,eye-term:
  126         description:
  127           The selection of HS_TX TERM reference voltage (U2 phy)
  128         $ref: /schemas/types.yaml#/definitions/uint32
  129         minimum: 1
  130         maximum: 7
  131 
  132       mediatek,efuse-intr:
  133         description:
  134           The selection of Internal Resistor (U2/U3 phy)
  135         $ref: /schemas/types.yaml#/definitions/uint32
  136         minimum: 1
  137         maximum: 63
  138 
  139       mediatek,efuse-tx-imp:
  140         description:
  141           The selection of TX Impedance (U3 phy)
  142         $ref: /schemas/types.yaml#/definitions/uint32
  143         minimum: 1
  144         maximum: 31
  145 
  146       mediatek,efuse-rx-imp:
  147         description:
  148           The selection of RX Impedance (U3 phy)
  149         $ref: /schemas/types.yaml#/definitions/uint32
  150         minimum: 1
  151         maximum: 31
  152 
  153     required:
  154       - reg
  155       - clocks
  156       - clock-names
  157       - "#phy-cells"
  158 
  159     additionalProperties: false
  160 
  161 required:
  162   - compatible
  163   - "#address-cells"
  164   - "#size-cells"
  165   - ranges
  166 
  167 additionalProperties: false
  168 
  169 examples:
  170   - |
  171     #include <dt-bindings/phy/phy.h>
  172 
  173     u3phy: xs-phy@11c40000 {
  174         compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
  175         reg = <0x11c43000 0x0200>;
  176         mediatek,src-ref-clk-mhz = <26>;
  177         mediatek,src-coef = <17>;
  178         #address-cells = <1>;
  179         #size-cells = <1>;
  180         ranges;
  181 
  182         u2port0: usb-phy@11c40000 {
  183             reg = <0x11c40000 0x0400>;
  184             clocks = <&clk48m>;
  185             clock-names = "ref";
  186             mediatek,eye-src = <4>;
  187             #phy-cells = <1>;
  188         };
  189 
  190         u3port0: usb-phy@11c43000 {
  191             reg = <0x11c43400 0x0500>;
  192             clocks = <&clk26m>;
  193             clock-names = "ref";
  194             mediatek,efuse-intr = <28>;
  195             #phy-cells = <1>;
  196         };
  197     };
  198 
  199 ...

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sys/contrib/device-tree/Bindings/phy/mediatek,xsphy.yaml