FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/phy/phy-rockchip-naneng-combphy.yaml

     # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
     %YAML 1.2
     ---
     $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
     $schema: http://devicetree.org/meta-schemas/core.yaml#
     
     title: Rockchip SoC Naneng Combo Phy Device Tree Bindings
     
     maintainers:
      - Heiko Stuebner <heiko@sntech.de>
    
    properties:
      compatible:
        enum:
          - rockchip,rk3568-naneng-combphy
    
      reg:
        maxItems: 1
    
      clocks:
        items:
          - description: reference clock
          - description: apb clock
          - description: pipe clock
    
      clock-names:
        items:
          - const: ref
          - const: apb
          - const: pipe
    
      resets:
        items:
          - description: exclusive PHY reset line
    
      rockchip,enable-ssc:
        type: boolean
        description:
          The option SSC can be enabled for U3, SATA and PCIE.
          Most commercially available platforms use SSC to reduce EMI.
    
      rockchip,ext-refclk:
        type: boolean
        description:
          Many PCIe connections, especially backplane connections,
          require a synchronous reference clock between the two link partners.
          To achieve this a common clock source, referred to as REFCLK in
          the PCI Express Card Electromechanical Specification,
          should be used by both ends of the PCIe link.
          In PCIe mode one can choose to use an internal or an external reference
          clock.
          By default the internal clock is selected. The PCIe PHY provides a 100MHz
          differential clock output(optional with SSC) for system applications.
          When selecting this option an externally 100MHz differential
          reference clock needs to be provided to the PCIe PHY.
    
      rockchip,pipe-grf:
        $ref: /schemas/types.yaml#/definitions/phandle
        description:
          Some additional phy settings are accessed through GRF regs.
    
      rockchip,pipe-phy-grf:
        $ref: /schemas/types.yaml#/definitions/phandle
        description:
          Some additional pipe settings are accessed through GRF regs.
    
      "#phy-cells":
        const: 1
    
    required:
      - compatible
      - reg
      - clocks
      - clock-names
      - resets
      - rockchip,pipe-grf
      - rockchip,pipe-phy-grf
      - "#phy-cells"
    
    additionalProperties: false
    
    examples:
      - |
        #include <dt-bindings/clock/rk3568-cru.h>
    
        pipegrf: syscon@fdc50000 {
          compatible = "rockchip,rk3568-pipe-grf", "syscon";
          reg = <0xfdc50000 0x1000>;
        };
    
        pipe_phy_grf0: syscon@fdc70000 {
          compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
          reg = <0xfdc70000 0x1000>;
        };
    
        combphy0: phy@fe820000 {
          compatible = "rockchip,rk3568-naneng-combphy";
          reg = <0xfe820000 0x100>;
          clocks = <&pmucru CLK_PCIEPHY0_REF>,
                  <&cru PCLK_PIPEPHY0>,
                  <&cru PCLK_PIPE>;
         clock-names = "ref", "apb", "pipe";
         assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
         assigned-clock-rates = <100000000>;
         resets = <&cru SRST_PIPEPHY0>;
         rockchip,pipe-grf = <&pipegrf>;
         rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
         #phy-cells = <1>;
       };

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