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     1 NVIDIA Tegra194 P2U binding
    2 
    3 Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
    4 Speed) each interfacing with 12 and 8 P2U instances respectively.
    5 A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE
    6 interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe
    7 lane.
    8 
    9 Required properties:
   10 - compatible: For Tegra19x, must contain "nvidia,tegra194-p2u".
   11 - reg: Should be the physical address space and length of respective each P2U
   12        instance.
   13 - reg-names: Must include the entry "ctl".
   14 
   15 Required properties for PHY port node:
   16 - #phy-cells: Defined by generic PHY bindings.  Must be 0.
   17 
   18 Refer to phy/phy-bindings.txt for the generic PHY binding properties.
   19 
   20 Example:
   21 
   22 p2u_hsio_0: phy@3e10000 {
   23         compatible = "nvidia,tegra194-p2u";
   24         reg = <0x03e10000 0x10000>;
   25         reg-names = "ctl";
   26 
   27         #phy-cells = <0>;
   28 };
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