ti,phy-am654-serdes.yaml

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    1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/phy/ti,phy-am654-serdes.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: TI AM654 SERDES binding
    8 
    9 description:
   10   This binding describes the TI AM654 SERDES. AM654 SERDES can be configured
   11   to be used with either PCIe or USB or SGMII.
   12 
   13 maintainers:
   14   - Kishon Vijay Abraham I <kishon@ti.com>
   15 
   16 properties:
   17   compatible:
   18     enum:
   19       - ti,phy-am654-serdes
   20 
   21   reg:
   22     maxItems: 1
   23 
   24   reg-names:
   25     items:
   26       - const: serdes
   27 
   28   power-domains:
   29     maxItems: 1
   30 
   31   clocks:
   32     maxItems: 3
   33     description:
   34       Three input clocks referring to left input reference clock, refclk and right input reference
   35       clock.
   36 
   37   assigned-clocks:
   38     $ref: "/schemas/types.yaml#/definitions/phandle-array"
   39   assigned-clock-parents:
   40     $ref: "/schemas/types.yaml#/definitions/phandle-array"
   41 
   42   '#phy-cells':
   43     const: 2
   44     description:
   45       The 1st cell corresponds to the phy type (should be one of the types specified in
   46       include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes lane function.
   47 
   48   ti,serdes-clk:
   49     description: Phandle to the SYSCON entry required for configuring SERDES clock selection.
   50     $ref: /schemas/types.yaml#/definitions/phandle
   51 
   52   '#clock-cells':
   53     const: 1
   54 
   55   mux-controls:
   56     maxItems: 1
   57     description: Phandle to the SYSCON entry required for configuring SERDES lane function.
   58 
   59   clock-output-names:
   60     oneOf:
   61       - description: Clock output names for SERDES 0
   62         items:
   63           - const: serdes0_cmu_refclk
   64           - const: serdes0_lo_refclk
   65           - const: serdes0_ro_refclk
   66       - description: Clock output names for SERDES 1
   67         items:
   68           - const: serdes1_cmu_refclk
   69           - const: serdes1_lo_refclk
   70           - const: serdes1_ro_refclk
   71 
   72 required:
   73   - compatible
   74   - reg
   75   - power-domains
   76   - clocks
   77   - assigned-clocks
   78   - assigned-clock-parents
   79   - ti,serdes-clk
   80   - mux-controls
   81   - clock-output-names
   82 
   83 additionalProperties: false
   84 
   85 examples:
   86   - |
   87     #include <dt-bindings/phy/phy-am654-serdes.h>
   88 
   89     serdes0: serdes@900000 {
   90       compatible = "ti,phy-am654-serdes";
   91       reg = <0x900000 0x2000>;
   92       reg-names = "serdes";
   93       #phy-cells = <2>;
   94       power-domains = <&k3_pds 153>;
   95       clocks = <&k3_clks 153 4>, <&k3_clks 153 1>,
   96                <&serdes1 AM654_SERDES_LO_REFCLK>;
   97       clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
   98       assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
   99       assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
  100       ti,serdes-clk = <&serdes0_clk>;
  101       mux-controls = <&serdes_mux 0>;
  102       #clock-cells = <1>;
  103     };

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sys/contrib/device-tree/Bindings/phy/ti,phy-am654-serdes.yaml