The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml

Version: -  FREEBSD  -  FREEBSD-13-STABLE  -  FREEBSD-13-0  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  l41  -  OPENBSD  -  linux-2.6  -  MK84  -  PLAN9  -  xnu-8792 
SearchContext: -  none  -  3  -  10 

    1 # SPDX-License-Identifier: GPL-2.0
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/pinctrl/fsl,imx8ulp-pinctrl.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: Freescale IMX8ULP IOMUX Controller
    8 
    9 maintainers:
   10   - Jacky Bai <ping.bai@nxp.com>
   11 
   12 description:
   13   Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
   14   for common binding part and usage.
   15 
   16 properties:
   17   compatible:
   18     const: fsl,imx8ulp-iomuxc1
   19 
   20   reg:
   21     maxItems: 1
   22 
   23 # Client device subnode's properties
   24 patternProperties:
   25   'grp$':
   26     type: object
   27     description:
   28       Pinctrl node's client devices use subnodes for desired pin configuration.
   29       Client device subnodes use below standard properties.
   30 
   31     properties:
   32       fsl,pins:
   33         description:
   34           each entry consists of 5 integers and represents the mux and config
   35           setting for one pin. The first 4 integers <mux_config_reg input_reg
   36           mux_mode input_val> are specified using a PIN_FUNC_ID macro, which can
   37           be found in <arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h>. The last
   38           integer CONFIG is the pad setting value like pull-up on this pin. Please
   39           refer to i.MX8ULP Reference Manual for detailed CONFIG settings.
   40         $ref: /schemas/types.yaml#/definitions/uint32-matrix
   41         items:
   42           items:
   43             - description: |
   44                 "mux_config_reg" indicates the offset of mux register.
   45             - description: |
   46                 "input_reg" indicates the offset of select input register.
   47             - description: |
   48                 "mux_mode" indicates the mux value to be applied.
   49             - description: |
   50                 "input_val" indicates the select input value to be applied.
   51             - description: |
   52                 "pad_setting" indicates the pad configuration value to be applied.
   53 
   54     required:
   55       - fsl,pins
   56 
   57     additionalProperties: false
   58 
   59 allOf:
   60   - $ref: "pinctrl.yaml#"
   61 
   62 required:
   63   - compatible
   64   - reg
   65 
   66 additionalProperties: false
   67 
   68 examples:
   69   # Pinmux controller node
   70   - |
   71     iomuxc: pinctrl@298c0000 {
   72         compatible = "fsl,imx8ulp-iomuxc1";
   73         reg = <0x298c0000 0x10000>;
   74 
   75         pinctrl_lpuart5: lpuart5grp {
   76             fsl,pins =
   77                 <0x0138 0x08F0 0x4 0x3  0x3>,
   78                 <0x013C 0x08EC 0x4 0x3  0x3>;
   79         };
   80     };
   81 
   82 ...

Cache object: 8e187347e517477611bb3ec572e7909f


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.